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In this paper, a novel Cascaded H-Bridge (CHB)-based multilevel inverter for symmetric/asymmetric configurations is presented. The proposed MLI can be utilized in medium-voltage applications such as electrical machine drives as well as grid connection of renewable energy resources. The proposed structure uses fewer count of semiconductor devices at the same voltage level in comparison with classic and advanced structures. Cascaded connection of the proposed basic cells leads to reduce complexity and increase efficiency of the proposed structure. In order to investigate the capability and superiority of the proposed structure, a comprehensive comparison is conducted between this structure and the advanced ones in terms of efficiency, switch and gate driver count, and total blocking voltage (TBV). The fundamental frequency switching method is employed to generate proper switching pulses. The performance of the proposed multilevel inverter is investigated by simulating in MATLAB/Simulink environment. The experimental implementation for proposed 15-level symmetric and 33-level asymmetric structures validates the correctness of simulation results. [ABSTRACT FROM AUTHOR]

Speed control of conventional low-voltage low-power induction motors (LV-LP-IMs) by two-level voltage source inverter (2LVSI) has some difficulties due to limitations of LV-LP-IMs especially insulation system. Besides, the use of multilevel inverters is not cost-effective either. In this paper, the new topology of reduced-switch-count three-level inverter with only eight switches is proposed for speed controlling of LV-LP IM. Eight-switch inverter is a newly three-level converter, which has the fewer number of switching devices, lower cost, smaller volume compared with the conventional three-level inverters, while it has sufficient switching vectors to speed control of IMs. In this paper, the structure and switching vectors of the eight-switch inverter are analyzed, and the direct torque control method based on the switching table and voltage balancing of the DC input voltage are presented for the LV-LP-IM speed control. Simulation results, considering different work conditions, are presented in order to validate finally the good performance of the proposed method. Moreover, the obtained results are compared with 2LVSI and conventional three-level inverters in different aspects. [ABSTRACT FROM AUTHOR]