Search

Normal naked 3D display have some defects,such as fixed viewing point,narrow viewing angle.In order to enhance the 3D performance,a 3D display system base on head tracking is introduced.In this system,a camera detects the position of observer's face,and a LC barrier moves the 3D viewing point toward the face simultaneously by changing its transmissive area.Thus the observer can receive good 3D images freely within the visual field of the camera.Because there is no meteyard for this wide viewing angle 3D display,this paper puts forward a test method.The experiment result proved the method is viable.

This paper introduces the principle,design solution and verification method of auto-stereoscopic display using an electric-field-driven LC lens.In order to realize the optimal 3D performance,professional software simulation and trail verification were used to adjust the design solution.It provides that a novel design about the electrode,specially discuss the distribution law of cell gap and refractive index,and the effect of retardation on 3D crosstalk.Using novel electrode structure and the rule of LC cell retardation to design electric-field-driven LC lens,3D crosstalk can be reduced to below 3%,the 3D module show excellent 3D image quality.It has very important significance to design and study the electric-field-driven LC lens.

The input macro block was used in the design of a signal receiver that turned LVDS signal into CMOS signal.The terminal resistors were analyzed;two methods of using terminal resistance were illustrated.The principle and the using of FPGA embedded resis-tance were emphatically analyzed.DDR technology was used,the method of using 3.5 times clock frequency to process 7 times data was researched and the frequency of data process was reduced.A serial to parallel converter was designed by using the data buffer.The method of data alignment and the two signal mapping formats supported by OpenLDI were analyzed.The data that conforms to the two standard data mapping format was output by using a data distributor.Combining with the characteristics of the Xilinx's FPGA clock processing macro block,the method of the clock recovering was researched.The periodic constraints,the special constraints,and the location constraints were used to improve the reliability of system.In order to improve the signal integrity of the whole circuit board and reduce the complexity of PCB layout,the method of inverting LVDS signals was studied.