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To better capture the phase information of single-phase power grids, a novel single-phase phase-locked loop method is proposed in this paper. The method uses a tracking differentiator as an orthogonal signal generator. Because the generator is sensitive to the input signal's frequency, the amplitudes of the tracking and differential signals may not be equivalent, causing a failed phase tracking. Therefore, the amplitude correction of the differential signal needs to be done. Then, the corrected differential signal and the tracking signal are both input to the phase detector. To further verify the practical feasibility of the method, the voltage sampling and phase tracking experiments were performed on a digital signal processor-based inverter experimental platform, which is aimed to simulate the grid. The experimental results show that the proposed algorithm has strong dynamic performance and steady-state performance under different states of the power grid, and the phase-locked method has a practical feasibility in single-phase grid-connected applications. [ABSTRACT FROM AUTHOR]

Multiple-valued logic such as ternary logic has attracted the digital system designers attention in recent years as it offers the benefits of reduced interconnects, higher operating speeds and smaller chip area. A goal of multi-threshold circuit design could be easily achieved by incorporating the scalable threshold voltage values of carbon nanotube field effect transistors (CNTFETs). This paper proposes a novel design of low-power and high-performance ternary adder and subtractor circuit design by combining the futuristic ternary and conventional binary logic design approaches. The simplified design of ternary to a binary decoder based on negative ternary inverter and positive ternary inverter outputs, and further transmission gate-based ternary multiplexer implementation facilitates the low power consumption and energy efficiency in the implementation of the complex arithmetic circuits. Extensive HSPICE simulations are conducted with the standard 32 nm CNTFET technology in order to evaluate the performance metrics of the realized circuits. According to the simulation results, proposed ternary adder and subtractor cells show the significant improvement in energy consumption (PDP) as compared to their counterparts under different test conditions. Moreover, the ripple adder structure is realized using the proposed adder circuit in order to test the practicability of given circuits in cascaded structures. [ABSTRACT FROM AUTHOR]

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates. [ABSTRACT FROM AUTHOR]

Leakage power consumption is a major technical problem faced in nanometer or deep submicron CMOS circuit technology. A new circuit technique based on 'lector stacking' is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in the idle and non-idle modes of operation for domino circuits. In this technique a p-type and an n-type leakage control transistor (LCT) are introduced between the pull-up and pull-down network, and the gate of one is controlled by the source of the other. For any combination of inputs, one of the LCTs will operate near its cut-off region and will increase the resistance between supply voltage and ground, resulting in reduced leakage current. Lector stacking retains the logic state during the idle mode as in the conventional footerless domino logic. Furthermore, the leakage current is suppressed at the output inverter circuit by adding a diode-footed transistor below the n-type transistor of the inverter, offering a more resistive path between supply voltage and ground.The proposed circuit technique for AND2, OR2, OR4, and OR8 circuits reduces the active power consumption by 13.66 % to 44.45 % and by 12 % to 33 % at the low and high die temperatures, respectively, compared to the standard footerless domino logic circuits. During idle mode for the same logic gates, 1.64 % to 79.39 % and 1.2 % to 35.19 % reduction of leakage current is observed with low and high inputs at 25 °C and 110 °C respectively. Similarly, during non-idle mode 0.94 % to 99.3 % and 1.57 % to 98.58 % is observed with low and high inputs at 25 to 110 °C, respectively, when compared to standard footerless domino logic circuits. [ABSTRACT FROM AUTHOR]

Using the results on transposition, it is shown that many of the realizations using current conveyors given for the various mutators in a recent paper by Soliman are intimately related. Some new types of mutators are introduced, and their realizations using two or three current conveyors are given. These results are then extended to the case of generalized impedance converters and inverters. [ABSTRACT FROM AUTHOR]

We present a high-speed differential clocked voltage switch logic inverter operating at ultra-low supply voltages (ULV). Simulated data for the new gate are presented and compared to modified clocked voltage switch logic (CVSL). Preliminary measurements for ULV gates are presented. The increase in speed for supply voltages below 300 mV for the ULV gate presented is between 10 and 20 times compared to modified CVSL logic. [ABSTRACT FROM AUTHOR]

In this work, we propose a novel procedure to generate and select threshold inverter quantized (TIQ) comparators for TIQ Flash ADCs. The new procedure generates more TIQ comparators than the procedure designed by Lee , Yoo, and Choi (LYC) (Proceedings of International Symposium on Quality Electronic Design, 2002). Two 6-bit TIQ Flash ADCs were designed, the LYC flash ADC, which selects its TIQ comparators using the current threshold selection algorithm, and the AC TIQ Flash ADC, which selects its TIQ comparators using the threshold selection algorithm proposed herein. Both ADCs were designed in $$0.5\,{\upmu }\hbox {m}$$ CMOS technology and compared against the process, voltage source, and temperature (PVT) variations. Proposed TIQ selection procedure allows the designer to select the optimum TIQ set for desired ADC. AC ADC has a DNL values ±0.015 LSB and INL values between $$\pm 0.0225$$ compared to ±0.1 LSB and 0.3 to −0.1 LSB for DNL and INL values of the LYC ADC. ENOB and SNDR for the AC were improved by at least $$31.3\%$$ compared to LYC ADC, at typical process settings. For process, voltage source, and temperature (PVT) variations, in overall the AC ADC has at least better the DNL values by at least $$22.5\%$$ and reduced INL values by at least $$35\%$$ . Over PVT variation, AC ADC has maintained ENOB value greater than 5.3 bits for all 16 variation corners. ENOB was improved by at least 1.5 bits over all corners. SNDR and SFDR were increased by at least 4 dB over the PVT corners. Proposed AC procedure shows scalability feature by generating extra threshold points for the $$65\hbox {-nm}$$ TIQ comparators. [ABSTRACT FROM AUTHOR]