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This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, a new high-gain operational transconductance amplifier (OTA) circuit is designed. The proposed circuit uses bulk-driven technique to reduce the required supply voltage while gain-boosting as well as positive feedback techniques are used to increase the gain of the circuit and compensate the gain reduction effect due to the use of bulk-driven transistors. The performance of the proposed circuit is simulated using 180-nm CMOS technology parameters and is optimized using an optimization algorithm for the main purpose of minimizing the power consumption of the circuit. Simulated performance of the proposed circuit for 1.2 V DC supply voltage shows 94.8 dB gain, 203-MHz bandwidth, and slew-rate of 365-V/µS while occupying die area of 1360 µm2. However, the proposed circuit is also designed for a low-voltage scenario with 0.75 V DC supply voltage that results in 73.7 dB gain, 131-MHz bandwidth, and slew-rate of 149-V/µS. [ABSTRACT FROM AUTHOR]

This paper describes a low-voltage phase-locked loop (PLL) design using a new calibration technique for low-power implantable biomedical systems. The proposed PLL uses a switching technique in the charge pump and a bulk-driven technique in the voltage-controlled oscillator (VCO) to reduce power consumption and operate at ultralow voltage. To compensate for the process variation, a calibration circuit is proposed to control the capacitor array of the VCO. This work was implemented in a 0.18- $$\upmu \hbox {m}$$ standard CMOS process with a 1.8-V supply voltage. The results show that the proposed PLL can operate from 402 to 405 MHz with a 0.7-V power supply and provides ten channel spaces for switching (where every channel has a bandwidth of 300 KHz) for biomedical system applications. At 405 MHz, the measured phase noise and reference spurs are $$-99.49$$ dBc/Hz at 1 MHz offset and $$-48.04$$ dBc, respectively. Furthermore, the measured root-mean-square jitter and peak-to-peak jitter are 9.93 and 82.03 ps, respectively. The total power consumption of the PLL is only 0.425 mW, and the active die area is 0.067 $$\hbox {mm}^{2}$$ . [ABSTRACT FROM AUTHOR]

The low-power current feedback instrumentation amplifier (CFIA) circuits using local feedback configuration are reported in the literature for biomedical applications. However, they have limitations such as low gain, higher area, and higher noise due to the need for higher source degeneration resistors (in tens to hundreds of kΩ), and higher minimum achievable bandwidth (in tens of kHz). In this paper, a low-power, low-noise CFIA using closed-loop configuration is proposed to overcome these limitations. It uses a folded cascode operational transconductance amplifier with a lower value of source degeneration resistor (in the order of few kΩ) in the input stage to reduce the noise without compromising the loop gain. As the bandwidth of the proposed CFIA is defined as unity-gain bandwidth of the CFIA's loop gain, it can be reduced below 10 kHz without increasing area. The proposed CFIA is designed and implemented in a 0.35 µm CMOS process for a current of 9.6 µA with a supply voltage of 3 V, and its performance is evaluated through simulation. It has a gain of 34 dB, total input-referred noise of 3 µVrms, and a noise efficiency factor of 3.81. It achieves a bandwidth of 8.8 kHz using a load capacitor which is more than four times smaller than that of local CFIA. It provides an input signal swing of 16 mVpp at THD of 1% and the CMRR of 118 dB. [ABSTRACT FROM AUTHOR]

In this paper, a novel ultra-low-power, low-voltage, ultra-high output resistance and uniquely high bandwidth (BW) femto-ampere current mirror is proposed. Pre-layout results with HSPICE in TSMC 0.18 $${\upmu }\hbox {m}$$ CMOS technology are given at 1.2 v power supply that prove such exceptional features of the proposed current mirror as: ultra-low consumed power of 1.56 $${\upmu }\hbox {w}$$ , ultra-high output resistance of 1.98 $$\hbox {T}\Omega $$ , very low output voltage of 91 mv and most exceptionally, the extra high BW of 26.5 MHz that is, so far, unique at such extra low minimum output current of 1.8 fA. Also, post-layout plus Monte Carlo simulation results are performed with CADENCE in the same abovementioned technology. Most favorably, this study also proves the same exceptional quality of the features as: the same ultra-low consumed power, fairly the same output voltage of 92 mv, ultra-high output resistance of 1.45 $$\hbox {T}\Omega $$ and still uniquely high BW of 17.5 MHz but at extra low output current of 5.5 fA. Good robustness of the proposed current mirror against PVT non-idealities is also proved by Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification. Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The comparator has a differential input overdrive resolution of under 1 mV and a response time which is scalable. The capacity for offset compensation trades with the bandwidth of the comparator through the size of the device channel areas (Width × Length) of the transistors. The static micropower consumed by the comparator from a 0.5 V supply voltage is under 10 μW, making it extremely suitable for miniaturized implantable biosensor devices. In addition, the comparator uses a single clock scheme for the sampled-data operations, which eliminates the need for special clock generation circuitry. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

A high-performance CMOS, fully balanced second-generation current conveyor (FBCCII) is proposed to exclusively use CCII circuits in integrated circuit applications. In the proposed circuit, a current folding technique is applied to a fully balanced version of transconductance amplifier. The proposed FBCCII consumes 84 μ W of power and has an open-loop gain of 47.83 dB with 62.9 ∘ of phase margin. The simulated input referred noise is 155 nV/ Hz @ 1 KHz and has a unity gain bandwidth of 39.8 MHz. A common mode feedback (CMFB) circuit is also proposed to improve the dynamic range of the proposed FBCCII circuit by 50 % as compared to the circuit with-out CMFB. The CMFB consumes 170 μ W of power and has a bandwidth of 60 MHz. The proposed circuit is simulated using standard 180 nm CMOS process operating at ± 0.5 V supply voltage. To verify the effectiveness of the approach, a fully differential variable gain amplifier with tunable gain from 0 to 30 dB is designed. Also, a bandpass filter with quality factor = 4 and bandwidth of 10 MHz is designed using the proposed FBCCII. A novel low-pass filter (LPF) using the proposed FBCCII is designed for bio-medical applications. The proposed LPF is a second-order filter with the cut-off frequency of 55 Hz and 121 nV/ Hz of input-referred noise. The LPF is designed at a supply voltage of ± 0.5 V, and the spurious free dynamic range of proposed LPF is 85 dB. The figure of merit of the LPF is 7.3 fJ. The layout area of the proposed FBCCII design is 6889 μ m 2 ( 83 μ m × 83 μ m ). [ABSTRACT FROM AUTHOR]

An energy-efficient capacitive switching scheme in successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed for biomedical applications. With novel sequence initialization and by reducing the up-switching steps during the A/D conversion, the average switching energy of this proposed procedure is reduced by over 98.7% compared with the conventional architecture after taking the parasitic capacitance into consideration. The number of capacitors in the proposed capacitor array is just 1/4 of that in the conventional switching scheme. Moreover, behavioral simulation performed in MATLAB for the 10-bit SAR ADC shows that the linearity performance of this proposed switching scheme is much better than that of previous architectures. [ABSTRACT FROM AUTHOR]

In most real-time DSP applications, high performance is a prime target. Here, performance may be interpreted as a combination of higher speed, lower power consumption, sufficient precision, and VLSI area efficiency. It has been experienced that efficient digital multiplication is a prerequisite for high-speed DSP applications. The MDLNS, which has similar properties to the classical LNS, is an alternative approach to conventional number systems for performing multiplication, through using parallel small adders. In addition, by applying recursive multiplication scheme, larger word length multiplication can be performed by use of several small multipliers. The concept of recursive multiplication can be applied to 2DLNS structures, resulting in more efficient digital multipliers. In this work, the recursive 2DLNS-based multipliers have been applied to FIR filter design. These applications demonstrate the superiority of our architectures in terms of VLSI area and power consumption. [ABSTRACT FROM AUTHOR]