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Several works report on overcoming the challenge of complex general-purpose signal processing algorithms that result in quick utilization of chip area resources (like FPGA in implementing system on chip or network on chip). However, with the advent of machine learning and deep learning algorithms, reducing this complexity and immense use of resources is a challenging task that can improve the system's performance in real time. One of the approaches is algorithm optimization, which consumes fewer resources and produces an equivalent performance. This approach may likely be accepted in less-sensitive applications, like voice or video processing. Recently, an optimized algorithm of correlation-less Wiener–Hopf-based adaptive channel equalizer is reported, in which the overall complexity of the system is reduced by employing a more compact way of weight optimization. This paper is the continuation of that work that reports the modification in the Steepest-Descent-based adaptive channel equalizer algorithm by keeping the autocorrelation matrix out of the algorithm. The proposed design is simulated and tested at equivalent spectral performance and produces comparable performance with fewer chip resources when translated on FPGA. The proposed design supports that algorithm-level optimization may be accepted extensively for the optimal hardware-based design of DSP systems. [ABSTRACT FROM AUTHOR]