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This work presents a PVT robust machine learning-based Voltage-controlled Oscillator (VCO) with an enhanced linearity range. The machine learning algorithm with PVT robustness is implemented digitally. Different from conventional methods, the proposed scheme does not require the VCO to be in working mode every time one needs the prediction of frequency. The proposed scheme uses the frequency to digital converter (FDC) output data as an input learning vector and uses a prediction block to predict the future frequencies. An 11-stage voltage-controlled oscillator with a machine learning algorithm is implemented in SCL 180 nm CMOS technology. The measurement results show that the proposed architecture is robust against PVT variations with an enhanced linearity range. Without a machine learning algorithm, the VCO's control voltage linearity range is 0.28 V to 0.40 V that increases to the range from 0.1 to 1.8 V after applying the proposed machine learning algorithm. The maximum gain variation of 3.71% is observed at FF with respect to the TT corner after applying the proposed machine learning algorithm. [ABSTRACT FROM AUTHOR]

In this work, a dual loop all-digital phase locked loop (ADPLL) is designed to obtain a fast locking, low power and low jitter for SoC and battery-operated applications. The high speed and high-resolution 4-bit flash time to digital converter (TDC) is also proposed to achieve low jitter and fast locking in ADPLL. The flash TDC uses a foreground calibration to make the ADPLL work robustly over PVT variations. In present work, fasting settling time of 1 μs and low power is achieved for proposed ADPLL owing to flash-based TDC and dual loop architecture. The proposed 4-bit flash TDC achieves a resolution of 6 ps. A low-phase noise voltage-controlled oscillator based on inverters is designed to obtain a reduced jitter in ADPLL. The ADPLL is implemented in a 180-nm SCL digital CMOS technology. The achieved phase noise of proposed ADPLL is − 128.2 dBc/Hz at an offset of 100 MHz. At an output frequency of 1.6 GHz, the periodic jitter of ADPLL is 7.8 ps, and power consumption is 6.5 mW. [ABSTRACT FROM AUTHOR]

Clinically, electrocardiogram (ECG) is a powerful tool for determining the health and functioning of the human heart. Faster detection and diagnosis of heart functioning would aid cardiologists to provide appropriate treatment to the patients (subjects). In this paper, the concept of fractional-order calculus is employed for noise cancellation and artifacts removal in ECG signal as fractional-order differentiator proved to provide more peculiar details about signals than an integer-order differentiator. In the proposed method, R-peaks are detected using Riesz fractional-order digital differentiator (RFODD) based on the differencing method. The differentiation operation enhances the high-frequency components of the signal. So, QRS complex which is a high-frequency component in ECG is accentuated and the R-peaks are detected using appropriate threshold technique. The proposed method is tested on Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia database, and the experimental results of the proposed method have achieved a sensitivity of 99.95%, positive predictivity of 99.949% and an error rate of 0.095%. ECG waveforms are analyzed on various fractional orders of RFODD, and their performance parameters, i.e., sensitivity, positive predictivity and error rate, are also calculated. [ABSTRACT FROM AUTHOR]