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In this paper, the design and simulation results of a general-purpose fuzzy logic controller, 5-bit digital inputs, and analog output are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect maximum, minimum, and mixed mode (both minimum and maximum) of the input voltages at the same time, an inference engine consisting of a min and max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, and the center of area is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, nine rules and one output designed in TSMC standard 0.18 µm CMOS technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters), and the layouts were extracted with Cadence Virtuoso v 5.1. The whole chip area is less than 0.7 mm2, inference speed of the controller is about 39.2 MFLIPS (fuzzy logic inference per second), and the average power consumption is 2.61 mW. [ABSTRACT FROM AUTHOR]

This paper presents a novel structure for implementing rational-powered membership functions (RPMFs), which are the extended forms of triangular/trapezoidal membership functions and those functions which are generated by applying linguistic hedges. The hardware realization of an RPMF consists of a triangular membership function generator circuit followed by a rational-powered generator module (RPGM). A novel fully programmable compact triangular/trapezoidal/s-shaped/z-shaped membership function generator with the ability to continuously change parameters is presented which is compatible with the proposed RPGM. A new method is introduced to implement the RPGM based on the approximation of the function ' x' by the functions square and square-rooter which are simply implemented in a current-mode analog approach based on the translinear principle, which leads to a design that is simple, and has high accuracy and less hardware usage, with a resulting lower chip area and lower power consumption. The designed circuit was simulated by an HSPICE simulator with level 49 parameters (BSIM3v3), and the simulation results show that the maximum power consumption of the RPGM is 800 μW, while the maximum RMS error is 1.25 %. Finally, layouts of the circuits prepared using Cadence software are presented. [ABSTRACT FROM AUTHOR]