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This paper reports the design of a 10-bit, high-resolution time-to-digital converter (TDC) based on Vernier residues amplification which is a novelty. This TDC architecture allows the measurement of wide time intervals with high picosecond-range resolution. The key benefits of the proposed TDC are that it reduces conversion jitter and provides more design flexibility to enhance matching performances of delay cells and thus reach high conversion linearity regardless of the process technology, which is a strong aspect of the approach. Simulations results show that the TDC achieves a timing resolution of 12 ps rms in a long 12.5 ns timing window, a low core power consumption of 4.8 mW and estimated differential and integral nonlinearities (DNL and INL) of 0.73 and 2.02 LSB with a standard deviation of 0.17 and 0.94 LSB respectively. The TDC, implemented in 0.13 mm CMOS technology, occupies a total silicon area of 1.83 $$\times $$ 2.23 mm $$^2$$ including pads. Such a TDC will find useful applications in tomographic systems, where several time-correlated single photon counting (TCSPC) channels need to be used in a massively parallel configuration such as in diffuse optical tomography or in time-of-flight positron emission tomography. [ABSTRACT FROM AUTHOR]