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Large datasets are often available for machine learning tasks. However, only very few contain labels for all the samples because labeling is a very labor-intensive process. Hence, large unlabeled datasets are available but inaccessible to traditional supervised learning methods. In this work, we combine two approaches to reduce the number of required labels. First, self-supervised learning (SSL) to utilize the large unlabeled dataset. SSL creates an encoder from those unlabeled samples that transforms the input into intermediate feature representations. Second, active learning is employed for the classification where labels are required. Active learning intelligently selects the most informative samples for manual labeling. Thus, it reduces the amount the labels required to achieve a high classification accuracy. The selected samples are used to train a brain-inspired hyperdimensional computing and random forest classifier. We demonstrate the outstanding performance of our approach with the example of wafer map defect pattern classification. It is a crucial diagnostic task helping to identify systematic problems in the manufacturing and improving yield. With our proposed method, a high 97% classification accuracy is achieved with only 6% of the labeled dataset for the first time. Our approach demonstrates the potential for training a machine learning model from less labeled samples by combining SSL with active learning.

Novel computer architectures like Compute-in-Memory (CiM) merge the memory and processing units, mimicking the human brain. Simultaneously, Hyperdimensional Computing (HDC) is emerging as a brain-inspired machine learning (ML) approach. Both developments hold promise for the realm of AI and computing, especially for genome-matching tasks, where large data movements overwhelm traditional von Neumann architectures. FeFET is one of the up-and-coming emerging technologies that promises to enable ultra-efficient and compact CiM architectures. However, the adoption of FeFETs is hindered by their 10 nm-thick Ferroelectric (FE) layer and process variation. Thus, calculations with FeFETs have errors (noise) that traditional ML genome-matching models cannot tolerate. To overcome these challenges, this work is the first one to i) present a reliable HDC framework (HDGIM) for highly-scaled (down to merely 3nm), multi-bit FeFET technology, ii) introduce temperature-thickness modeled noise from FeFET to the HDC system, and iii) extensively define the memorization capacity of HDC hyperparameters in order to evaluate the performance before deployment theoretically. Our novel HDC learning framework iteratively uses two models: a full-precision 32-bit HDC model, an ideal model for training, and a reduced bit-precision by a novel quantization method for validation and inference. Our results demonstrate that highly-scaled FeFET, realizing 3-bit and even 4-bit, can withstand any modeled noise given high dimensionality during inference. Considering the noise during model adjustment improves the inherent robustness by almost 9% on the 4-bit case.

Reliability is one of the key concerns in circuit design. The circuit must be able to tolerate transistor degradation to sustain reliability against timing failure. Whether a transistor is degraded due to noise, aging, or poor manufacturing, a circuit must uphold a timing error-free functionality over its entire projected lifetime. Transistors are hardened (designed stronger than necessary) to tolerate these degradations. However, hardening (e.g., widening the transistors) comes at the cost of additional area and power. Hence, it is necessary to identify and selectively harden specific transistors within a circuit. In this work, transistors that prolong a circuit’s delay when they are degraded are termed “susceptible”, and thus, are to be hardened. Identifying the susceptible transistors within a circuit is a complex task, for example, Monte Carlo circuit simulations require days to identify susceptible transistors in a single circuit. Consequently, current solutions are costly in terms of time and limited in their application. Instead, machine learning (ML) can offer a fast (inference in seconds) and universal (applicable to unseen circuits) alternative. However, traditional ML techniques struggle with inference on topology-based problems, while recent graph neural networks (GNNs) excel in these applications. Therefore, this work presents the first ML to classify susceptible transistors with GNNs. We use GNNs, specifically Graph Attention Networks (GAT), because the topology of the cell strongly affects how each transistor degradation affects performance. For instance, series-connected transistors amplify their impact, while parallel-connected ones can offset each other’s influence. Our GAT-based approach employs a heterogeneous graph in combination with GAT’s attention mechanism to capture the circuit’s topology and its impact on the analysis. Our evaluation demonstrates the capability of our approach to classifying transistors according to their impact within the ASAP7 standard cell library’s standard cells in mere 0.04 s (compared to days of Monte Carlo simulation time) while achieving 80.4% accuracy on unseen circuits.

With the continuous scaling in technology nodes, the transistor self-heating effect (SHE) emerges as a growing threat to circuit reliability. Increasingly confined transistor structures and advanced materials exacerbate thermal insulation, concealing temperature hotspots in the transistor’s channel. Without the consideration of these increased temperatures, reliability effects such as aging will be underestimated, putting the circuit at risk. In this work, we propose a novel design flow that enables designers to extract accurate SHE temperatures at the circuit level and harden their design with SHE-aware synthesis. Our approach employs customized standard cell libraries to convey SHE information and guide logic synthesis toward SHE-resilient designs. Using our approach, we demonstrate effective suppression of SHE in circuits by up to 50%, trading off improved SHE resilience against timing, power, and area goals. In addition, our SHE analysis allows for accurate estimation of timing guardbands, reducing unnecessary pessimism of conventional approaches by over 50%.

Solving constraint satisfaction problems (CSPs) is in high demand for various applications. SNN serves as a competitive annealing machine that can solve the CSP more efficiently than well-known Metropolis sampling and Hopfield networks. NVM-based crossbars with analog Integrate and Fire (IF) neurons can evolve the state of SNN to solve CSP more efficiently. However, analog computations inherently suffer from imprecisions in NVM cells, e.g., current variation, OFF-state leakage, and temperature-induced drift. We are the first to analyze the impacts of various memory technologies, including 2T-NOR, FeFET, WOx ReRAM, and HfOx ReRAM, on solving the Ising model, Sudoku, and Traveling-salesman-problem (TSP). The results show that both 2T-NOR Flash and FeFET with normalized standard deviation( ${\sigma }/{u}$ ) $< 5\%$ and ON-OFF ratio $>$ 1000 are both ideal candidates as synapse devices at room temperature, while other devices suffer from the effects of current variation and OFF-state leakage, which would require the neuron circuits to have infeasible membrane capacitance size. However, the drift of cell current and the reduction of the ON-OFF ratio drops the success rate as the temperature increases. The success rate of solving TSP drops by 60% and 90% while the temperature increases from 300K to 358K for 2T-NOR and FeFET, respectively. Throughout the simulation, we show that the transistor-based memory is suggested to be a synapse device. Yet, we also find that the tolerance of temperature is inevitable under limited capacitance. Exploration of temperature-tolerated design of circuit and memory design is still in demand for future works.

The pivotal issue of reliability is one of the major concerns for circuit designers. The driving force is transistor aging, dependent on operating voltage and workload. At the design time, it is difficult to estimate close-to-the-edge guardbands that keep aging effects during the lifetime at bay. This is because the foundry does not share its calibrated physics-based models, comprised of highly confidential technology and material parameters. However, the unmonitored yet necessary overestimation of degradation amounts to a performance decline, which could be preventable. Furthermore, these physics-based models are computationally complex. The costs of modeling millions of individual transistors at design time can be exorbitant. We propose the use of a machine learning model trained to replicate the physics-based model, such that no confidential parameters are disclosed. This effectual workaround is fully accessible to circuit designers for the purposes of design optimization. We demonstrate the model’s ability to generalize by training on data from one circuit and applying it successfully to a benchmark circuit. The mean relative error is as low as 1.7%, with a speedup of up to $20\times $ . Circuit designers, for the first time ever, will have ease of access to a high-precision aging model, which is paramount for efficient designs. In contrast to existing work, our approach takes the full switching activity into account to model recovery effects. This work is a promising step in the direction of bridging the gap between the foundry and circuit designers.

In this work, we are the first to investigate and model the characteristics of a commercial 5nm FinFET technology from room temperature (300K) all the way down to cryogenic temperature (10K). We focus on SRAM circuits demonstrating how cryogenic temperatures impact their power, delay, and reliability. SRAM memories are key components in quantum read-out and control circuits, and therefore characterizing their key figure of merits when building cryogenic-CMOS circuits is essential. To achieve that, we first measure the electrical characteristics of nFinFET and pFinFET devices from 300K down to 10K. Then, we carefully calibrate the cryogenic-aware BSIM-CMG, which is the first industry-standard compact model for FinFET technologies designed for cryogenic temperatures. This enables us to reproduce the experimental data in which SPICE simulations come with an excellent agreement with the measurements. Using our well-calibrated transistor models, we simulate a complete 32-bit SRAM memory array, including a write driver, sense amplifier, pre-charger, and output latch. Then, we investigate how cryogenic temperatures impact the SRAM read and write delays at several stages during the operation, as well as the power and energy. For a more comprehensive analysis, we perform our studies for different SRAM types covering high-density, high-performance, and low-voltage cells. All transistor and SRAM analyses are performed at both room temperature and cryogenic temperature to obtain detailed comparisons revealing the exact role that cryogenic temperature plays in SRAMs. All in all, we demonstrate that commercial 5nm FinFET is indeed suitable for cryogenic-CMOS circuits required in quantum processors, revealing that the performance of SRAMs at 10K does improve while power and energy consumption are reduced. Nevertheless, SRAM reliability is more challenging in which noise margins need to be carefully engineered to remain sufficient at 10K.

Computing the similarity between two binary strings is a frequently used operation in cryptography, machine learning, and other areas. The Hamming distance is a simple yet costly to compute similarity metric. A common way is to XOR both binary input strings and then count the number of 1s. Especially the latter popcount part is inefficient with purely digital circuits. In this paper, a novel analog circuit is proposed to compute the Hamming distance in an ultra-efficient way. Contrary to the major trend in the state of the art, no emerging technology is required. Instead, the unique feature of the mature FDSOI transistor technology is exploited for the first time to perform analog-based similarity calculation. Thanks to the additional back gate available in this technology, the transistor’s threshold voltage can be modulated by more than 1 V. Through this key feature, an ultra-efficient analog computing is realized, replacing the inefficient digital popcount traditionally built from expensive adder tree structures. The design is evaluated with an FDSOI transistor model calibrated with industrial measurements. The energy-delay product is at least 24 $\times $ smaller than purely digital implementations and the transistor count is reduced by over 2.6 $\times $ .

The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von Neumann principles. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as a novel structure that offers for the first time disturb-free read operation along with $>\,\,\mathrm {10\,\,\times }$ larger memory window (MW) compared to conventional FeFETs. However, all the before-mentioned variations are amplified in such a new structure. This work analyses the impact of temperature variation for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels, and compared to conventional FeFET. Through our cross-layer framework, we demonstrate the severe impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even Hyperdimensional Computing is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.

Machine learning (ML)-driven standard cell library characterization enables rapid, on-the-fly generation of cell libraries, opening the door for extensive design-space exploration and other, previously infeasible approaches. However, the benefits of ML-based cell library characterization are strongly limited by its high demand in training data and the costly SPICE simulation required to generate the training samples. Therefore, efficient learning strategies are needed to minimize the required training data for ML models while still sustaining high prediction accuracy. In this work, we explore multiple active and passive learning strategies for ML-based cell library characterization with focus on aging-induced degradation. While random sampling and greedy sampling strategies operate with low computational overhead, active learning considers the performance of ML models to find the most valuable samples for training. We also introduce a hybrid approach of active learning and greedy sampling to optimize the trade-off between reduction in training samples and computational overhead. Our experiments demonstrate an achievable training data reduction of up to 77% compared to the state of the art, depending on the targeted accuracy of the ML models.