1. Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales
- Author
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Ebrahimi, M., Evans, A., Tahoori, Mehdi B., Seyyedi, R., Costenaro, E., Alexandrescu, D., Department of Agricultural Biotechnology, Payam-e-Noor University Karaj Branch, IMA (KARLSRUHE UNIV.), Karlsruhe Univ., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Karlsruhe Institute of Technology (KIT), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)
- Subjects
analytical-testing ,010302 applied physics ,Pacs 85.40 ,Soft Error ,020208 electrical & electronic engineering ,0103 physical sciences ,analysis-flow ,0202 electrical engineering, electronic engineering, information engineering ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,01 natural sciences ,020202 computer hardware & architecture - Abstract
International audience; Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.
- Published
- 2014