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This paper deals with the process of optimizing embedded digital signal processor (DSP) systems. Although efficiency goals differ in every system, optimization normally focuses on program execution speed, memory usage, and power consumption. DSP are a specialized type of microprocessor that handles certain types of algorithms extremely efficient for real-time signal processing. Compilers perform optimization techniques that are both machine dependent and independent. A particularly important generic optimization technique is loop unrolling. The trade-off in loop unrolling is that it requires more instruction code, and more registers and cache space for data. Because DSP are number crunchers by nature, their assembly instruction sets may include some instructions for mathematical operations used often in algorithms. Assembly operations require different lengths of time due to memory-access delays and differences in parallel function units. When the compiler predicts these conditions, it can force the processor to wait by inserting no operation cycles into the instruction stream. Software pipelining inherently improves execution speed, but it may not be possible if unnecessary dependencies exist. Direct memory access control is essential to the operation of high-performance DSP, allowing data transfers to proceed with little or no intervention from the processor core.