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Over the past decade, the demands for 3D NAND flash memory devices have been increased tremendously due to ever growing digital economics in consumer electronics, data centers, IOT, healthcare and automotive industries. The growth is further accelerated during the recent Covid period. The industry was able to keep up the scaling roadmap by stacking more memory cell in vertical direction to realize higher bit density at reducing cost per Gig-bit. Unlike devices scaling via feature size reduction, 3D NAND flash vertical stack scaling puts challenges mostly on film deposition and etch. Among many steps, high aspect ratio (HAR) ONON channel hole formation modules remained the most critical steps. Forming billions of perfect channel holes from top to bottom without distortion and twisting is the grand challenge. Besides individual etch and deposition module optimization, deposition and etch Co-optimization (DECO) could provide new opportunities. In this paper, we will present a summary of the recent progress in the approaches and the benefits of DECO as potential pathways to overcome the HAR ONON patterning. We will discuss the ONON Tier Optimization for profile control to reduce the top bowing and enlarge the bottom CD. We will introduce a sacrificial liner approach to prevent top CD enlargement at deeper etch depth. We will also discuss new mask materials for better etch selectivity and profile control to enable the scaling roadmap.

Phase change materials (PCM) have emerged as the leading candidate for next generation non-volatile storage class memory as demonstrated by the commercialization of 3D Cross Point memory. More recently, PCM memories have been explored for non-von Neumann system architectures with potential applications in neuromorphic computing. To accelerate the widespread adoption of PCM technology, better understanding of the unit processes and its interactions is needed to cost effectively produce high fidelity PCM devices. Challenges in creating cross point PCM architectures are significantly different from more dominant technologies such as DRAM and 3DNAND. From a device perspective, the PCM composition is sensitive to crystallization temperature, which translates to potentially large changes in the switching resistance for small changes in composition. From a material perspective, phase change chalcogenides readily etch in various plasma etch chemistries with the many etch chemistries exhibiting bulk composition changes. Furthermore, slight changes in the PCM composition can be removed by wet clean. In this regard, one of the main process challenges is to not etch chalcogenides laterally in order to maximizing the device volume. Finally, from a structural perspective, PCM are relatively soft with Young’s modulus that can be 3x smaller than materials found in DRAM/3DNAND stacks (e.g. Si, SiOx). Soft chalcogenides can lead to increased line bending, especially when the chalcogenide is at the bottom of the stack. As a result, post wet clean pattern collapse and line bending from film stress can be challenging to manage. To meet the material and structural challenges, we developed an integrated system combining dry etch, wet clean, and deposition process modules. Comprehensive understanding of each process module as well as the interactions of different process modules has been obtained. We will present some holistic process solutions combining dry etch, wet clean, and deposition to deliver collapse free, high fidelity PCM structures.

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