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The demand for the high-density integrated memories is growing along with the scaling of the transistor technology nodes. To fabricate the reliable devices in advanced technologies, optimization of several process steps is necessary [1]. The capacitor, which is commonly a MIM (Metal-Insulator-Metal) module finds its application as a basic storage device in memories, filters, voltage limiters etc. The MIM module is also considered as an integral part of memory technologies such as DRAM, FeRAM, and RRAM. The MIM modules should demonstrate reliable operation through better performance and efficiency. And, it is realized through the parameters related to MIM module such as, low leakage current, less variability with respect to capacitance, high quality factor Q, lower defect density, low parasitic capacitance and many others [2]. Reactive-ion-etching plays a very important role in BEOL integration of MIM devices. The MIM module is created by dry etching through the MIM stack. Related to RRAM (Resistive Random Access Memory) applications the MIM stack consists of an additional buffer layer such as Ti or Hf [3]. These layers are easily oxidizable and the etching step could oxidize them from the sidewalls. Also, the residuals of the metal if remain on the sidewall could lead to leaky devices. Hence, an etch process which is not well optimized could damage the devices and in turn pose a threat to their functionality and reliability [4]. An improved MIM stack etch process is beneficial to reduce the above-mentioned damages. Several techniques were used in the past to cover the MIM devices with dielectric materials like SiO2 and SiN, which protects the devices from further process steps involved in the fabrication procedure [5]. In this work we demonstrate the effect of the improved etch process with a combination of SiNO spacers and encapsulation techniques for TiN/Ti/HfO2/TiN stacks. This stack is most popularly used in RRAM and, in this work, it is integrated into the BEOL of the 250 nm CMOS technology at IHP. To test the performance of the devices, the MIM stack was fabricated in three different approaches. In the first approach, photoresist is used as a mask to etch the MIM stack, the second one uses TiN hard mask and the third one uses TiN hard mask etch in addition to creation of SiNO spacers after the TiN/Ti etch. The encapsulation of MIM modules with SiNO is implemented in all the three approaches mentioned above. Special device structures with the TiN/Ti/HfO2/TiN stack are fabricated to test the variability of the MIM parameters on the entire wafer. Additionally, the switching operation was tested by means of DC voltage sweeps on the MIM RRAM devices which includes, forming, reset and set steps followed by 50 cycles of reset and set processes. The devices associated with the improved fabrication process steps exhibited less variability in terms of leakage current, capacitance and Q-factor values along the entire wafer. This reduction in the variability of the parameters corresponding to the MIM devices could be used for emerging applications. References G.S. Kar, A.Fantini, Y.Y. Chen, V. Paraschiv, B. Govorenau, H. Hody, N. Jossart, H.Tielens, S. Brus, O. Richard, T. Vandeweyer, D.J. Wouters, L. Altimime, M. Jurczak, i n Symposium on VLSI Technology (VLSIT), 2012 IEEE, pp. 157-158 E. Pérez, A. Grossi, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and Ch. Wenger, in MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), 2018 IEEE, pp. 1-3 E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, and Ch. Wenger, Solid-State Electronics, (2019) V. B. Naik, J. H. Lim, K. Yamane, D. Zeng, H. Yang, N. Thiyagarajah, J. Kwon, N. L. Chung, R. Chao, T. Ling, K. Lee, in International Reliability Physics Symposium (IRPS), 2019 IEEE, pp. 2C-2 Y.S. Chen, H.Y. Lee, P.S. Chen, P.Y. Gu, W.H. Liu, W.S. Chen, Y.Y. Hsu, C.H. Tsai, F. Chen, M.J. Tsai, and C. Lien, Electron Device Letters, Vol. 32, Issue: 3, pp 390-392 (2011)

The process of epitaxial SiGe layers are getting attractive as they offer a variety of advanced microelectronics devices compatible with silicon processing technology [1-3]. The large research effort of the last decade has focused on the growth of high quality strained SiGe layers. In particular, SiGe superlattice containing high Ge concentration is demanded in order to improve performances of the devices. Recently, IHP has achieved a significant breakthrough in SiGe/Si MQW processing technology [4]. The developed high quality of superlattice of SiGe/Si MQW structure containing 50% Ge has been successfully processed (Fig. 1) and presented as a potential thermistor material with its high performance for uncooled microbolometer applications [5]. The prototype of thermistor device with 50% Ge in SiGe wells exhibited an outstanding TCR of -5.5 %/K and a K1/f value of 3.4 × 10-15 for 200 µm× 200 µm pixel size, respectively, showing a concurrent achievement of a very high TCR and a low 1/f noise performance. One of the main challenge of SiGe/Si MQW structures is the high resistance values including high Ge concentration makes it difficult to integrate as a detector material in a complete microbolometer device. Large pixel resistances cause not only high noises and hence lower sensitivity but also a challenge to design and maximize the performance of the ROICs [6, 7]. A method to optimize and tune the resistance of the detector material in microbolometers is in-situ doping of quantum well layers in order to enhance the combined detector and ROIC performance. In [8], Boron (B) doping level in SiGe quantum wells are optimized in order to keep the pixel resistance of the thermistor in acceptable values for an ROIC design. B doping of SiGe MQWs is used for the resistance tuning of the detector. The main challenge of the method is simultaneous achievement of enough doping in the SiGe region of the MQWs while keeping the barrier intrinsic silicons non-doped. The initial pixel resistance of 3 period of SiGe/Si MQWs with 50% Ge concentration of 21 MΩ is reduced 210 kΩ for 25 × 25 µm2 pixel size by the optimization of in-situ B doping level in SiGe layers of the MQW stack [8]. The optimized B doping density of ~1 × 1018 cm-3 in SiGe wells did not cause any significant change in the TCR value whereas the 1/f noise performance is even enhanced due to the in-situ doping process. All the aforementioned results shows the successful demonstration of intrinsic thermistor based on SiGe/Si MQWs including 50% Ge with an acceptable pixel resistances. Although the successful demonstration of SiGe MQWs has been performed for high performance microbolometer applications, a full integration of the high performance SiGe/Si MQW based detector into a standard CMOS process is still challenging. SiGe/Si MQW process requires higher temperatures than the temperature budget of the post processing of CMOS process. Therefore, the transfer of the optimized detector structure to a CMOS/BiCMOS wafer needs a special layer transfer process (i.e. wafer bonding). More critically, due to the vertical working principle mechanism of the detector device, there is a challenge for full integration of the optimized detector structure into standard BiCMOS process because the suspended detector device needs to be contacted by both sides In this work, the recent progress on SiGe/Si type high performance detector structures will be presented. The process optimization of the detector by means of high TCR, low 1/f noise and appropriate resistance will be detailed. The method of integrating the developed SiGe/Si MQW structures into a 130 nm BiCMOS process will be provided. The integration method is based on the oxide-oxide fusion bonding of ROIC and detector wafer followed by post processing of the bonded wafer stack. The details of thermal conductance optimization of the microbolometer together with the mechanical stress optimization, required for the suspended detector device, will also be given. Finally, the low-pressure hermetic packaging of the microbolometer structure will also be proposed. Figure 1