Because of their superior performances to amorphous silicon (a-Si) semiconductors, amorphous oxide semiconductors have been attracting considerable attentions as backplanes for liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs). For mass production, the back channel etch (BCE)-type TFTs have considerable advantages owing to lesser process steps, lesser parasitic capacitances and shorter channel length than those of the etch stop layer (ESL)-type TFTs. However, the BCE-type TFTs often suffer from the unstable TFT operation against the transfer conditions and the various stress conditions due to the back channel damages to the oxide semiconductor [1-3]. Our study clearly demonstrates an addition of annealing process (post-annealing) that acts as recovery annealing is effective between SiNx deposition and SiOx deposition as passivation layer for the BCE-type TFTs application. The post-annealing effect to improve the stability of the BCE-type TFTs is investigated. The Oxide TFTs were fabricated on glass substrates with gate electrodes and gate insulator. The IGZO (Indium Gallium Zinc Oxide) thin film was deposited on the substrate by DC magnetron sputtering. Next, source and drain electrodes were formed by wet-etching process using a H2O2-based etchant. The passivation layer composed of double layered SiNx/SiOx was formed by PECVD, and some samples were treated with the aforementioned post-annealing at 300 ℃ in air during the passivation layer formation. It is confirmed that the stability under the negative bias thermal illumination stress (NBTIS) of the BCE-type TFTs with the post-annealing was superior to that of the BCE-type TFT without the post-annealing. In order to clarify the variation of the chemical composition of the IGZO thin film surfaces due to the post-annealing, X-ray Photoelectron Spectroscopy (XPS) was examined as well as electronic state analysis such as photoinduced transient spectroscopy (PITS) [4,5]. [1] G. Wang, Z. Song, X. Xiao, and S. Zhang; AM-FPD 2015 Symposium Digest, pp.111. [2] M. Nag, A. Bhoolokam, S. Steudel, A. Chasin, K. Myny, J. Maas, G. Groeseneken, and P. Heremans; Jpn. J. Appl. Phys, Vol. 53, No. 11, 111401 (2014). [3] R. Zhan, C. Dong, P.-T. Liu, and an H.-P. D. Shieh; Microelectronics Reliability, 53, pp.1879 (2013). [4] J. C. Balland, J. P. Zielinger, M. Tapiero, J. G. Gross, and C. Noguet; J. Phys. D: Appl. Physics, Vol. 19, No. 1 (1986). [5] A. Hino, Y. Takanashi, H. Tao, S. Morita, M. Ochi, H. Goto, K. Hayashi, and T. Kugimiya; J. Vac. Sci. Technol. B 32 (2014) 031210. Figure 1