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We present a comprehensive study of area scaling for 22nm-logic-node routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and double-patterning (DP) regimes. For each candidate route pitch (88-56nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel 'source/design optimization' technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.