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Hybrid bonding is an indispensable technique for the 3D integration of electronic systems. Cu-to-Cu interconnections and SiO2-to-SiO2dielectric layers should be bonded simultaneously in the wafer-to-wafer bonding process. In this study, sequential plasma activation (SPA) including O2plasma, N2plasma, and N radical is investigated for low-temperature bonding of Cu and TEOS SiO2at 200°C. The SPA bonding improves the bond strength to more than 1 J/m2compared to the conventional single gas plasma activation bonding. The surface analysis indicates that SPA forms oxynitrides on TEOS SiO2surface and Cu oxide with adsorbed water on the Cu surface, facilitating the bonding interface formation. The presented technique will contribute to the hybrid bonding applications at lower temperatures.

Invention of IC was driven by "Tyranny of Numbers", a challenge implied by large number of interconnects in a large-scale system. Modern ICs integrate many miles of wiring and billions of contacts. Moore's Law, however, will die, and we cannot rely just on integration on a chip. A revolutionary solution of the connection problem is now needed for further integration. Our proposal, as More-Than-Moore, is to replace mechanical connection using wiring, solder, and connectors by electrical one using near-field coupling. Transmission Line Coupler by electromagnetic coupling for module connection and ThruChip Interface by inductive coupling for chip stacking is presented and discussed in this paper.

This paper presents a wireless inter-chip link using inductive coupling, namely ThruChip Interface (TCI). TCI is a digital CMOS circuit solution in a standard CMOS technology. It is much less expensive than TSV (Through Silicon Via) but bears comparison in performance. Delay time and energy dissipation will scale down by scaling device size and chip thickness. As the inductive coupling enables interface among chips under different supply voltages, TCI is suitable for heterogeneous integration. A 90nm 8-core processor under 1.0V power supply and two 65nm SRAM's under 1.2V power supply are stacked and AC-coupled by TCI at 19.2Gb/s. Power dissipation and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps respectively, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface.