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This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channel-first schemes with improved process control, while tackling critical etch-layout dependences.

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

Low-frequency noise is studied in planar high-k-metal/gate (HKMG) last pMOSFETs in order to study the impact of a post-HfO2 deposition SF6-plasma or heat treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-k layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2 layer.

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. The best results could be achieved by combination of both.

A dry-wet patterning process for La2O3/HfO2-containing high-k/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-k layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-k layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

The replacement of poly-silicon by metallic compounds in the gate stack leads to the search of metals with suitable work function. However, it is observed that thermal budget has a large influence on the effective work functions of several metals. In this paper, we investigated the possible modification of the chemical states by physical analysis techniques (XPS, ERD, SIMS) by studying investigating the chemistry of the high-k oxide/metal interface. We show that in the case of the TiN/TaN/HfO2/SiO2/Si stack, several modifications occur upon 1000{degree sign}C N2 annealing: Increase of the nitrogen content of the TaN, interdiffusion of the Ti and TaN, and formation of Ta2O5 at the TaN/HfO2 interface.

To facilitate selective removal of the gate dielectric towards the gate electrode, wet etch characteristics of HfSiOx and HfSiOx(N) in acidified HF solutions were determined as function of several process parameters. Etch behavior of Hf- silicates was found to be little influenced by the various CVD deposition processes. The top part (0-2 nm) of thick Hf- silicate layers etched similar to as-deposited thin layers (< 2nm) while the bulk part was etching significantly slower. However, etch rates were strongly dependent on composition (lower for Hf-rich silicates). Also, the removal rate of HfSiOx (N) was mainly depending on the amount of incorporated nitrogen and crystallization temperature. Thermally nitrided layers were easier to remove compared to plasma nitrided layers. Post nitridation anneals at high temperature in nitrogen environment decreased the etch rate. After removal, Hf concentrations below 1e11 at/cm2 for most of the HfSiOx(N) layers under study were observed after a short (typically a few seconds) etch process in a single wafer spin cleaning tool.

The etch properties of PVD TaN used as a metal gate electrode have been found to be dependent on its crystalline microstructure. As found by XRD, the initially amorphous TaN crystallizes at temperatures above 500C. The crystallization results in lower resistivity (decreased by 13%), and lower etch rate in BCl3 plasma (decreased by 24%). The different crystalline microstructure can manifest itself in different etch results when the same etch process is applied for gate stacks that contain the same TaN but were subjected to different thermal budget.

This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channel-first schemes with improved process control, while tackling critical etch-layout dependences.

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

Low-frequency noise is studied in planar high-k-metal/gate (HKMG) last pMOSFETs in order to study the impact of a post-HfO2deposition SF6-plasma or heat treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-k layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2layer.

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. The best results could be achieved by combination of both.

A dry-wet patterning process for La2O3/HfO2-containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

The replacement of poly-silicon by metallic compounds in the gate stack leads to the search of metals with suitable work function. However, it is observed that thermal budget has a large influence on the effective work functions of several metals. In this paper, we investigated the possible modification of the chemical states by physical analysis techniques (XPS, ERD, SIMS) by studying investigating the chemistry of the high-k oxide/metal interface. We show that in the case of the TiN/TaN/HfO2/SiO2/Si stack, several modifications occur upon 1000{degree sign}C N2 annealing: Increase of the nitrogen content of the TaN, interdiffusion of the Ti and TaN, and formation of Ta2O5 at the TaN/HfO2 interface.

To facilitate selective removal of the gate dielectric towards the gate electrode, wet etch characteristics of HfSiOx and HfSiOx(N) in acidified HF solutions were determined as function of several process parameters. Etch behavior of Hf- silicates was found to be little influenced by the various CVD deposition processes. The top part (0-2 nm) of thick Hf- silicate layers etched similar to as-deposited thin layers (< 2nm) while the bulk part was etching significantly slower. However, etch rates were strongly dependent on composition (lower for Hf-rich silicates). Also, the removal rate of HfSiOx (N) was mainly depending on the amount of incorporated nitrogen and crystallization temperature. Thermally nitrided layers were easier to remove compared to plasma nitrided layers. Post nitridation anneals at high temperature in nitrogen environment decreased the etch rate. After removal, Hf concentrations below 1e11 at/cm2 for most of the HfSiOx(N) layers under study were observed after a short (typically a few seconds) etch process in a single wafer spin cleaning tool.

The etch properties of PVD TaN used as a metal gate electrode have been found to be dependent on its crystalline microstructure. As found by XRD, the initially amorphous TaN crystallizes at temperatures above 500C. The crystallization results in lower resistivity (decreased by 13%), and lower etch rate in BCl3 plasma (decreased by 24%). The different crystalline microstructure can manifest itself in different etch results when the same etch process is applied for gate stacks that contain the same TaN but were subjected to different thermal budget.