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Your search keyword '"Souriau, Laurent"' showing total 12 results
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12 results on '"Souriau, Laurent"'

1. Key Issues for the Development of a Ge CMOS Device in an Advanced IC Circuit

Author

Meuris, Marc M., primary, Martens, K., additional, De Jaegar, B., additional, Van Steenbergen, J., additional, Bonzom, Renaud, additional, Caymax, Matty R., additional, Houssa, M., additional, Kaczer, Ben, additional, Leys, Frederik, additional, Nelis, Daniel, additional, Opsomer, Karl, additional, Pourghaderi, A. M., additional, Satta, A., additional, Simoen, Eddy R., additional, Terzieva, Valentina, additional, Souriau, Laurent, additional, Bellenger, F., additional, Brammertz, Guy, additional, Nicholas, G., additional, Scarozza, M., additional, Huyghebaert, C., additional, Winderickx, Gillis, additional, Loo, Roger, additional, Clarysse, Trudo, additional, Conard, Thierry, additional, Bender, Hugo, additional, Benedetti, Alessandro, additional, Todi, R., additional, Delabie, A., additional, Hellin, David, additional, Van Daele, Benny, additional, Sioncke, Sonja, additional, Mertens, Paul W., additional, De Meyer, Krtistien, additional, Van Elshocht, Sven, additional, Vandervorst, Wilfried, additional, Zimmerman, Paul, additional, Brunco, David P., additional, and Heyns, Marc M., additional

Published
2019
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8. Germanium: The Past and Possibly a Future Material for Microelectronics

Author

Brunco, David P., primary, De Jaeger, Brice, additional, Eneman, Geert, additional, Satta, Alessandra, additional, Terzieva, Valentina, additional, Souriau, Laurent, additional, Leys, Frederik E., additional, Pourtois, Geoffrey, additional, Houssa, Michel, additional, Opsomer, Karl, additional, Nicholas, Gareth, additional, Meuris, Marc, additional, and Heyns, Marc, additional

Published
2007
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10. Defect Aspects of Ge-on-Si Materials and Devices

Author

Claeys, Cor, Eneman, Geert, Wang, Gang, Souriau, Laurent, Loo, Roger, and Simoen, Eddy

Abstract

An overview is given of the defect aspects with respect to Ge-on-Si materials and devices, with emphasis on the impact of post-growth thermal budget on the structural and electrical epi-layer characteristics. The observations on annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations (TDs). It is also demonstrated that for the present processing conditions, the leakage current of Ge CMOS compatible p+n junctions becomes independent of the TD density at about 10E7/cm2.

Published
2009

11. High Hole Mobility SGOI Substrates Obtained by the Germanium Condensation Technique

Author

Souriau, Laurent, Nguyen, Tuan, Loo, Roger, Terzieva, Valentina, Caymax, Matty, Cristoloveanu, Sorin, Meuris, Marc, and Vandervorst, Wilfried

Abstract

Thin SGOI substrates with Ge content from 42 to 93% have been produced by the Ge condensation technique and full structural characterization has been carried out. In a second step, the electrical properties of these substrates have been analyzed by the pseudo-MOSFETs technique which allowed the determination of the carrier low field mobilities as well as the density of fixed charges in the buried oxide (BOX) and the density of interface traps at the BOX-SiGe film interface. Optimization of intermediate anneals in argon during the condensation process has made the production of high crystalline quality and high mobility substrates possible (up to 400 cm2/Vs for a 93% SGOI). Opposite trends were observed for holes and electrons: while the hole mobility is increasing with increasing Ge content, the electron mobility decreases. Moreover, the density of interface traps and the density of oxide charges were found to increase with increasing Ge content.

Published
2008

12. Key Issues for the Development of a Ge CMOS Device in an Advanced IC Circuit

Author

Meuris, Marc M., Jaegar, De, Steenbergen, Van, Bonzom, Renaud, Caymax, Matty R., Kaczer, Ben, Leys, Frederik, Nelis, Daniel, Opsomer, Karl, Simoen, Eddy R., Terzieva, Valentina, Souriau, Laurent, Brammertz, Guy, Winderickx, Gillis, Loo, Roger, Clarysse, Trudo, Conard, Thierry, Bender, Hugo, Benedetti, Alessandro, Hellin, David, Van, Benny, Sioncke, Sonja, Mertens, Paul W., Meyer, Krtistien De, Van, Sven, Vandervorst, Wilfried, Zimmerman, Paul, Brunco, David P., and Heyns, Marc M.

Abstract

Passivation of the channel in the gate stack is the most important problem for introducing another material than silicon into the channel of CMOS devices. In order to compare the mobility values of different passivation techniques, we propose to use a parameter, which is a proportional to the drive current of the transistor. We call this parameter the channel mobility value and it is calculated from the transistor equation. This channel mobility value can be used to benchmark more consistently the different passivation techniques on germanium or other semiconductor materials. A second issue for CMOS scaling on Ge is the poor performance of nMOS devices and there seems no solution in sight for this problem. Therefore we promote the investigation of technologies to allow the introduction of III-V materials on Ge to make nMOS devices in III-V devices complementary with Ge pMOS. A third key issue is the development of a manufacturable and low defect density germanium-on-insulator (GeOI) technology on 200mm and larger substrate sizes.

Published
2006

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