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A novel SRAM cell expected to increase the SRAM integration density is proposed and demonstrated with a test structure in this work. It consists of three elements: a MOSFET, a load, and a bistable PNPN diode as the storage element. The PNPN diode and the load can be integrated in a vertically stacked structure, which can be scaled as small as the design rules allow, and the MOSFET has a small gate width, so the new SRAM cell offers the possibility for much higher integration density compared to the conventional 6-T SRAM cell. Moreover, the low holding current of the PNPN diode and the soft “punch-through” design provide the potential for low power consumption and high speed applications.