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Information about several papers discussed at the International Symposium on Physical Design held in April 2006 in San Jose, California is presented. New chip design at 65 nanometers where temperature, voltage and process variations have dramatic impact on chip timing, manufacturability and yield were offered during the symposium. It also featured several authors from the University of California in Los Angeles and International Business Machine Research who received ISPD 2006 Best Paper Award.

The article cites that Georgia Tech University, IBM Corp., IMEC, the Fraunhofer Institute, Tohoku University and TSMC presented papers on through-silicon via technology (TSV) at the Institute of Electrical and Electronics Engineers Inc. 2008 International Interconnect Technology Conference in Burlingame, California. TSV technology is seen as a solution to a looming interconnect crisis which could emerge by 2009.