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The article discusses the papers presented at the International Solid-State Circuits Conference (ISSCC) held in February 2009 at the San Francisco Marriott hotel in California. One of the papers considers the introduction of Intel Corp.'s Nehalem-EX server CPU, a 2.3 billion-transistor member of its 45-nm Nehalem family. Meanwhile, another paper shows the technique described by Hideaki Saito, a principal researcher at NEC Corp., for stacking a memory chip using direct aluminum-to-copper links.

The article reports on the two technical papers presented at the recent International Interconnects Technology Conference in San Francisco, California. The papers indicated the semiconductor researchers' power-saving techniques as they scale chips to smaller sizes. Researchers from Intel Corp. showed direction on how to optimize repeater and logic transistor technologies, as well as improving repeater insertion methods and applying three-dimensional integration. Another paper from Georgia Institute of Technology suggested the use of carbon nanotubes to address some of the challenges of gigascale-integration interconnects.

Focuses on the presentation of ferro-electric memories at the International Electron Devices Meeting in San Francisco, California. Overview of the research paper from Texas Instruments, Agilent Technologies and Ramtron International; Description of volt embedded-Ferrous random access memory technology; Details of the paper of Fujitsu.

Information on the discussion of designs for biomedical devices at the International Solid-State Circuits Conference in San Francisco, California is presented. German researchers presented an artificial silicon retina consisting of 232 electrodes, that will be implanted in few patients in 2007 by Intelligent Medical Implants AG, one of the co-developers. Maurits Ortmanns, an assistant professor who discussed the paper, revealed that patients with the implant will have real visual reception.

The article reports that Rambus Inc. will reveal a technique for delivering Input/Output with power rates of 2.2 milli-watts per gigabit per second, at the 2007 International Solid-State Circuits Conference in San Francisco, California. In its prepared paper, Rambus Inc. will describe a 6-Gbit/second serializer/deserializer transceiver at 2.2 mW/Gbit/s in 90-nanometer process technology. The company believes that the technology would achieve power reduction and would deliver high performance.

The article highlights IBM Corp.'s (IC) emphasis on electronic frequency as presented at the 2006 International Solid-State Circuits conference in San Francisco, California. IC design engineers delivered three papers that described the pending Power6 microprocessor, aimed at the company's own pSeries servers. The 65-nanometer Power6 will be launched in the four- to five-gigahertz range when servers begin shipping in 2007.

Provides information on the 50th International Solid-State Circuits Conference that will be held on February 10, 2003 in San Francisco, California. Theme of the keynote speech that will be delivered by Gordon Moore, chairman emeritus of Intel Corp.; Paper sessions; Panels; Workshops.

Reports on the holding of the 48th International Electron Devices Meeting in San Francisco, California, from December 8-11, 2002. Topics of the opening papers session; Product introductions.

The article reports on the presentation of two papers at the International Solid-State Circuits Conference in San Francisco, California that discussed advances in medical test equipment. Shu-Jen Han at the Stanford University presented his work on a DNA detector that would lower the size and cost of DNA microarray test equipment. Long-Shen Fan at the National Tsing Hua University in Taiwan discussed development of a desktop magnetic resonance imaging system for cellular-level research.

The article previews the International Solid-State Circuits Conference to be held from February 5-9, 2006 in San Francisco, California. The record number of papers that will be presented at this landmark event will topple records in chip density, performance and sophistication. But amid the sound of shattering records are more subtle themes like gradual shifts in architectural thinking, the quiet emergence of entirely new technologies in bioscience and organic circuits and the incredible continuity of silicon CMOS. The CMOS theme will be sounded in the first keynote of the plenary session.