1. A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
- Author
-
Pasquale Tommasino, Pietro Monsurro, Giuseppe Scotti, Alessandro Trifiletti, and Francesco Centurelli
- Subjects
Materials science ,Computer Networks and Communications ,lcsh:TK7800-8360 ,Topology (electrical circuits) ,02 engineering and technology ,Hardware_PERFORMANCEANDRELIABILITY ,BiCMOS ,Inductor ,law.invention ,Footprint (electronics) ,Frequency divider ,law ,0202 electrical engineering, electronic engineering, information engineering ,Hardware_INTEGRATEDCIRCUITS ,Current-mode logic ,Electrical and Electronic Engineering ,frequency divider ,low power ,business.industry ,Current Mode Logic ,SiGe HBT design ,020208 electrical & electronic engineering ,Transistor ,lcsh:Electronics ,Electrical engineering ,020206 networking & telecommunications ,Biasing ,Hardware and Architecture ,Control and Systems Engineering ,Signal Processing ,business - Abstract
A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 ×, 65 &mu, m2 on silicon.
- Published
- 2020