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This paper deals with a circuit in which a total of eight ports made of two sets of four ports are mutually separated and in which the input from one port is delivered to four ports of another set with equal amplitudes with a certain phase relationship. This circuit is called the eight-port hybrid circuit and is an extension of the characteristics of a conventional (four-port) 3-dB hybrid to the case of eight ports. A circuit configuration is proposed by means of four branch-line-type 3-dB hybrids. First, by taking advantage of the symmetry of the circuit, an analysis is carried out. The relationship to be satisfied by the characteristic admittances of each branch line is determined. The frequency characteristics of the scattering matrix elements are presented. Next, a design method for broadening the bandwidth is given for the matching circuits to be attached to each port and quarter wavelength transmission lines connecting each hybrid. A relative bandwidth of about 20 percent is realized. Also, the test circuit is measured and the validity of the design method is confirmed. The present circuit is advantageous in that the circuit configuration is possible on one side of the substrate by means of strip lines and all eight ports are directed outward so that connection with other circuits is simplified. [ABSTRACT FROM AUTHOR]

To improve the speed and accuracy of the CMOS flash A/D converter using a copper-type comparator, an analysis has been perforated for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage. A model has been developed in which the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoretical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either 0 or V ref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. It is found that the product of the ladder resistor and the comparator input capacitance between adjacent terminals must he less than 5 × 10-13 F·Ω in order to obtain an 8 bit A/D converter with 20 MS/s. Variation is decreased if the mid-point of the ladder resistor is fixed. For instance, when the midpoint is fixed, the product of the ladder resistor and the comparator input capacitance is allowed to increase up to 2 × 10-12 F·Ω. [ABSTRACT FROM AUTHOR]