Search

A control scheme to achieve wafer-to-wafer temperature uniformity in the reaction tube used for oxidation, diffusion, or annealing during semiconductor processes is proposed. In the analytical model, self-radiation loss, radiation between neighboring wafers, radiation from the tube wall, and thermal diffusion on a wafer surface are taken into account. The temperature monitoring points were the inlet, middle, and outlet of the reaction tube. The analysis indicates that if the tube wall temperatures at the inlet and outlet are 6 percent higher than that at the center of the tube, the wafer-to-wafer temperature becomes uniform. In the experiment, taking the silica tube temperature as the tube wall temperature, the increase in the temperatures at the inlet and outlet must be 5.6 percent to achieve wafer-to-wafer temperature uniformity, while it should be 6.9 percent if the temperature of the secondary tube is considered to be the tube wall temperature. Experiment results verify the effectiveness of the model. At the same time, the tube wall temperature is assumed to be influenced not only by the temperature of the silica tube but also by that of the secondary tube. The model predicts that the wafer temperature increased by 1°C if the tube wall temperature is increased as described in the foregoing. However, in the experiment, the wafer temperature increases by 1.6°C at most [ABSTRACT FROM AUTHOR]

In the high-temperature process of semiconductors, the temperature distribution on the wafer surface during the procedures of the wafer insertion into the removal from the oxidation or diffusion furnace is important in determining the density of the dislocation due to the thermal stress and the uniformities of both the oxide thickness and the diffusion depth. As the size of a wafer and the density of integration increase, the analysis of the thermal transient characteristics becomes more important. This paper analyzes the model of the temperature transient characteristics proposed previously and describes the transient characteristics on a wafer by measuring the temperature distribution on a wafer in a furnace using an infrared radiometer. The simulation for a case where a wafer of 150 mm in diameter is inserted into furnace at a speed of 20 cm/min indicates that the temperature variation on a wafer at every moment is as high as 150°C. This result agrees with the experimental result within an accuracy of 25°C. When the insertion speed is 100 cm/min, the temperature variation increases by 20 to 30 percent and is maintained until the wafer reaches the high-temperature zone. This is caused by the increase in the rate of temperature change with time due to the radiation from the tube wall which is the external heat source. This tendency is more noticeable for wafers located at the middle row. [ABSTRACT FROM AUTHOR]

The nonuniform temperatures that develop over silicon wafers on insertion and removal from the furnaces used in the oxidation and diffusion processes of semiconductor fabrication are one factor in reduced yields. For example, because of temperature differences in the oxidation process there are thermal stresses and differing thermal hystereses over the wafer surface which degrade the uniformity of the oxide layer formed. The most pronounced temperature differences, occurring when the wafers are inserted into the furnace, develop mainly because of the effect of the boat μg which supports the wafers. Since the heat capacity of the boat is much greater than that of the wafers, during the slower rise in the boat temperature radiant heat exchange with the wafer bottoms keeps the temperature of the bottoms lower than the temperature of the wafer tops, which are almost unaffected by the boat. This transient in the wafer temperature depends on such process parameters as the boat insertion speed, the ratio between the wafer and furnace reactor tube diameters, and the wafer spacing. In order to analyze this temperature characteristic the process is modelled and the results of numerical simulation are compared with experiment. The model for the wafer temperatures inside the furnace is a system of coupled partial differential equations for the mostly radiant heat fluxes of the boat and wafers. With an insertion speed of 2 m/sec, both the experimental data and the model give a maximum temperature difference over the wafer surface of 230°C near the end of insertion, thus confirming the model. [ABSTRACT FROM AUTHOR]

In semiconductor fabrication it is difficult to form channels with precisely controlled lengths, even when using plasma etching which itself is highly precise. This is because of fluctuations in the processes preceding the etching, as, for example, in the developed resist dimensions. This paper proposes a method for controlling channel lengths which relies on an optimized over-etching, the extra etching time after the normal etch completion depending on the variation in resist dimension, etc. In the method a phenomenological model is set up for the rate of change of channel length as a function of the resist dimension and etching cross section, and the polysilicon layer thickness and Its phosphorus doping density as determined by sheet resistance. The model coefficients are estimated by a Kalman filter on wafer and lot measurement data. The results of production line experiments with the present method show a reduction in channel length variation by one-half compared with the previous uncontrolled method. [ABSTRACT FROM AUTHOR]