Search

This paper proposes a new construction method for error correcting codes and its decoding method. The code proposed in this paper (code KI) maps the symbol of error correcting codes over a certain finite field onto another class of error correcting codes. In this sense, the code can be interpreted as a generalization of the conventional error correcting codes. The proposed codes have the following features. (1) The codes are fundamentally suitable for unequal error protection (UEP) codes. (2) Maximum likelihood decoding can be used efficiently in part. (3) There exists a coding parameter enabling improvement of performance in comparison to the conventional codes in the region of small SN ratios. In this paper, the principle of the proposed codes, encoding method, decoding method, and performance are discussed. Further, it is shown that the proposed codes provide a chance to discuss the problems of efficiency enhancement, synchronization characteristics, and unequal error correcting characteristics from a new point of view. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(11): 65–74, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.1155 [ABSTRACT FROM AUTHOR]

This paper proposes a design method for a bandpass prefilter with a recursive structure and a few multipliers. Since the system function for this prefilter is in a closed form, the design is simple. In this design, interpolations are used repeatedly. As a model filter, RRSs of low-pass or high-pass types with a recursive structure are used. Since the method is based on the interpolation technique, multipliers are required for removal of unwanted passbands, although the number of multipliers is small. In the realized prefilter, the center frequency can be chosen arbitrarily as long as it is at the point equally dividing a unit circle. By means of examples, the effectiveness of the present prefilter is confirmed for reducing the number of multipliers and adders. [ABSTRACT FROM AUTHOR]

With recent advances in digital technology, it is now easy to copy digital content. As a result, unauthorized copying of content is widespread and copyright protection has become a serious issue. One solution to this problem is electronic watermarking, for which various techniques have been proposed. However, since no method of evaluation of the robustness of electronic watermarking methods has been established, it is difficult to compare various methods. This paper presents an analysis of the correlation-based electronic watermarking method in which a pseudo-random sequence is embedded as a watermark into the transform coefficients of the image and watermarking is detected by correlation. A method of evaluation is also proposed. Based on the proposed method, an electronic watermarking method using discrete wavelet transforms is proposed. Finally, based on the results, methods for improving the performance of the watermarking method are discussed. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(11): 1–12, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10093 [ABSTRACT FROM AUTHOR]

active filter with a single operational amplifier is effective and practical not only because of its low cost and low-power dissipation, but also because of its easiness of compensation in meeting conditions required for a high-frequency-band filter. Based on such a filter structure, this paper proposes a high-frequency-band active RC filter using a single operational amplifier which can be operated ideally at a frequency band, the open-loop gain can be approximated by GB/s. The proposed circuit is simple, and can realize a lowpass, bandpass or highpass filter function by choosing an arrangement of its input and output terminals. The pole sensitivity is analyzed in relation to the gain-band- width (GB) product. A bandpass filter having a significantly low pole-sensitivity was obtained. [ABSTRACT FROM AUTHOR]

This paper proposes a spectral estimation method in which the criterion in the unbiased estimation of the log spectrum is applied to a spectral model represented by the generalized cepstrum. An iterative algorithm for solving the minimization problem is given, the convergence is shown to be quadratic, and the stability of the model solution is ensured. In the proposed method, the spectral model can be varied continuously from the all-pole spectrum to that represented by the cepstrum, according to the value of the parameter γ. The spectral model has the ad- vantages of both the all-pole and cepstral representations, and it has been observed that the analysis-synthesis system based on the generalized cepstral representation generates higher-quality speech than that of conventional systems. This paper discusses, from several viewpoints, a method proposed for spectral estimation and demonstrates the usefulness of the method by examples of synthesized signal and analysis of natural speech. The method includes the linear prediction and the unbiased estimation of the log spectrum, and can be considered as a unified approach to linear prediction and cepstral methods. [ABSTRACT FROM AUTHOR]

We propose a new parallel processor architecture which is suitable for use with current VLSI technology. We term this architecture FMPP (Functional Memory type Parallel Processor architecture). The integration density of this architecture can be increased in accordance with the regular nature of its structure in a manner similar to memory chips. We regard the simple logic function equivalent to the roughly 100 transistors of each RAM word added, as a 1-word bit serial processor. We take the memory to be an SIND parallel computer system consisting of simple processors for many numbers as there are RAM words. This architecture implements a simple parallel algorithm for solving several combinational problems and combinational optimization problems. We call this algorithm a parallel exhaustive search (PRE), which does not require much scheduling of intercommunication and task assignment. In this paper, we have chosen the knapsack problem as an example of a combinational optimization problem and evaluate a realistic circuit size and execution time for a PES. We can construct a system composed of 10,000 or 100,000 processor using current or future CMOS technology. We show that the parallel algorithm is more than 1,000 times faster than sequential algorithms. [ABSTRACT FROM AUTHOR]

This paper proposes a universal learning machine (ULM) that absorbs information from environments and acquires an ability to process information professionally according to the environments. Additionally, it applies this information to the recognition of the English type-letters that are high-densely printed in magazines, books, etc. A window is applied on a black and white image gathered through an image scanner so that only a letter and a head part of the succeeding letter can be observed. Appropriately fixing a distance that measures the similarity between the window images, the recognizer utilizing the ULM searches for some one of the most similar window images to the current from among the window images memorized in the past. Then the recognizer loads the records accompanying it to display for a user the reading of the designated letter and the boundary between this letter and the succeeding letter. The user commands whether the recognizer should revise the memory or continue the recognition process. If the command is for revision, the content of revision is memorized in the form of a binary tree while part of the content memorized in the past is deleted to prevent overflow in system memory capacity. A theoretical evaluation of the performance of the ULM and an experimental evaluation on the English type-letter recognizer actually constructed are performed. [ABSTRACT FROM AUTHOR]

High transport capacity, high safety, and high reliability are required of train control systems in the high-density operational sections. The conventional systems operate as follows. The presence of a train is detected at each fixed section. Based on a decision as to whether or not the train should progress into the section, the velocity of the train is calculated by a centralized control system on the ground, and the result is communicated to the automatic train control device (ATC) of the train. It is difficult to realize high-density transport by this mechanism. This paper proposes an autonomous decentralized ATC system (D-ATC), which works as follows. Each train detects its own position. Only the position at which to stop is communicated from the ground to the train, and the velocity of the train is determined and controlled autonomously on the basis of this instruction. Then, an assurance technology is proposed in which trains with D-ATC are introduced stepwise without disturbing the operation of the whole system, and their testing in on-line operation is assured while they coexist with trains with the existing ATC. The on-train integration and the on-train separation technologies are presented as two methods of stepwise introduction and are evaluated from the viewpoint of assurance. Based on the results obtained in this study, a practical application was performed in the train control system of the JR East Yamanote/Keihin Tohoku line. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(10): 46–56, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20194 [ABSTRACT FROM AUTHOR]

High-dimensional neural networks, such as complex neural networks and three-dimensional neural networks, have been proposed. They are capable of learning high-dimensional motions, which cannot be done by real-valued neural networks. In this paper, high-dimensional neurons are defined as vectors, and certain high-dimensional neural networks, such as complex neural networks, quaternary neural networks, and three-dimensional exterior neural networks, are unified in terms of a vector representation. It is shown that all of these types have the common feature of alternating matrices. The inverse quaternion neural network has the ability to learn rotations. In addition, it is shown that the proposed model cannot represent all rotations in neural networks that are higher than three-dimensional, and that the inverse quaternary neural network has a partial ability to learn rotations. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(11): 38–45, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10072 [ABSTRACT FROM AUTHOR]

The virtual reality technique has been widely applied to various problems, as a human interface technique emphasizing vision. Recently, practical use of tactile/force feedback device realizing the haptic (tactile) interface has been considered, recognizing the importance of tactile sensation. Consequently, the authors have proposed a “touch and see” haptic vision/active vision-tactile idea, aiming at the automatic construction of a virtual space simulator faithful to the real world from the observed image, by using the haptic interface [6–8]. Aiming at the automatic construction of the virtual object manipulation simulator faithful to the real world based on haptic vision, this paper proposes a method of automatic extraction of the 2D constraints among objects on the horizontal plane. A method is also proposed to describe the mutual constraints among objects in the 3D space, based on the hierarchical structure of the extracted 2D mutual constraints. It is verified from the results of experiments using the haptic vision system that the horizontal support relation among rigid objects is extracted faithfully to the real world. It is also verified that the system is useful in realizing virtual object manipulations which are faithful to the real world, by using extracted mutual constraint among objects as an input to a virtual space simulator with a haptic interface. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(11): 75–85, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10130 [ABSTRACT FROM AUTHOR]

This paper discusses the general-purpose LSI for multiplex transmission equipment, and proposes a high-speed program-controlled multiplex circuit (P-MUX) which combines the time slot assigned by hardware logic and the general-purpose bit-processing processor. Its construction is discussed. The functions required for P-MTJX are described first, and then the construction of those functions is discussed. Especially, for the high-speed time-slot assigner which forms the basis for P-MUX, the single-memory system and the separate memory system are compared. It is shown that the separate memory system is suited to the proposed LSI, since the internal processing speed is improved drastically. The multiphase access is employed for the interface to the general-purpose bit-processing processor. This makes it possible to perform the prograimning without considering the access timing, thereby improving the programming efficiency. Finally, the experimental LSI and the structure of the interface converter based on the proposed LSI are discussed. [ABSTRACT FROM AUTHOR]