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Non-invasive fetal electrocardiography (NI-ECG) is based on the acquisition of signals from electrodes on the mother's abdominal surface. This abdominal ECG (aECG) signal consists of the maternal ECG (mECG) along with the fetal ECG (fECG) and other noises and artifacts. These records allow the acquisition of valuable and reliable information that helps ensure fetal well-being during pregnancy. This paper proposes a procedure based on principal component analysis (PCA) to obtain a single-channel master abdominal ECG record that can be used as input to fetal heart rate extraction techniques. The new procedure requires three main processing stages: PCA-based analysis for fECG-component extraction, polarity test, and curve fitting. To show the advantages of the proposal, this PCA-based method has been used as the feeding stage to a previously developed clustering-based method for single-channel aECG fetal heart rate monitoring. The results obtained for a set of real abdominal ECG recordings from annotated public aECG databases, the Abdominal and Direct Fetal ECG Database and the Challenge 2013 Training Set A, show improved efficiency in fetal heart rate extraction and illustrate the benefits derived from the use of such a master abdominal ECG channel. This allows us to achieve proper fetal heart rate monitoring without the need for manual inspection and selection of channels to be processed, while also allowing us to analyze records that would have been discarded otherwise. [ABSTRACT FROM AUTHOR]

The security of Industrial Internet of Things (IIoT) systems is a challenge that needs to be addressed immediately, as the increasing use of new communication paradigms and the abundant use of sensors opens up new opportunities to compromise these types of systems. In this sense, technologies such as Trusted Execution Environments (TEEs) and Hardware Security Modules (HSMs) become crucial for adding new layers of security to IIoT systems, especially to edge nodes that incorporate sensors and perform continuous measurements. These technologies, coupled with new communication paradigms such as Blockchain, offer a high reliability, robustness and good interoperability between them. This paper proposes the design of a secure sensor incorporating the above mentioned technologies—HSMs and a TEE—in a hardware device based on a dual-core architecture. Through this combination of technologies, one of the cores collects the data extracted by the sensors and implements the security mechanisms to guarantee the integrity of these data, while the remaining core is responsible for sending these data through the appropriate communication protocol. This proposed approach fits into the Blockchain networks, which act as an Oracle. Finally, to illustrate the application of this concept, a use case applied to wine logistics is described, where this secure sensor is integrated into a Blockchain that collects data from the storage and transport of barrels, and a performance evaluation of the implemented prototype is provided. [ABSTRACT FROM AUTHOR]

Collaborative manufacturing is a key enabler of Industry 4.0 that requires secure data sharing among multiple parties. However, intercompany data-sharing raises important privacy and security concerns, particularly given intellectual property and business-sensitive information collected by many devices. In this paper, we propose a solution that combines four technologies to address these challenges: Attribute-Based Encryption for data access control, blockchain for data integrity and non-repudiation, Hardware Security Modules for authenticity, and the Interplanetary File System for data scalability. We also use OpenID for dynamic client identification and propose a new method for user revocation in Attribute-Based Encryption. Our evaluation shows that the solution can scale up to 2,000,000 clients while maintaining all security guarantees. [ABSTRACT FROM AUTHOR]

The development of devices for the Internet of Things (IoT) requires the rapid prototyping of different hardware configurations. In this paper, a modular hardware platform allowing to prototype, test and even implement IoT appliances on low-cost reconfigurable devices is presented. The proposed platform, named Dracon, includes a Z80-clone microprocessor, up to 64 KB of RAM, and 256 inputs/outputs (I/Os). These I/Os can be used to connect additional co-processors within the same FPGA, external co-processors, communications modules, sensors and actuators. Dracon also includes as default peripherals a UART for programming and accessing the microprocessor, a Real Time Clock, and an Interrupt Timer. The use of an 8-bit microprocessor allows the use of the internal memory of the reconfigurable device as program memory, thereby, enabling the implementation of a complete IoT device within a single low-cost chip. Indeed, results using a Spartan 7 FPGA show that it is possible to implement Dracon with only 1515 6-input LUTs while operating at a maximum frequency of 80 MHz, which results in a better trade-off in terms of area and performance than other less powerful and less versatile alternatives in the literature. Moreover, the presented platform allows the development of embedded software applications independently of the selected FPGA device, enabling rapid prototyping and implementations on devices from different manufacturers. [ABSTRACT FROM AUTHOR]

Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device. [ABSTRACT FROM AUTHOR]

Different types of fill-level measurement systems exist in the market, but most of them imply some type of intrusion in the tank itself. In this paper, a reconfigurable system based on sound resonance for measuring the fill-level of a tank from the exterior is presented. A relation between sound resonance frequencies and the content of the tank has been found, especially as the tank gets closer to being full. A prototype has been created using reconfigurable technologies combined with wireless communications in order to control the system from an ad hoc application. With this prototype, the fill-level of different tanks has been measured with good resolution, especially when the tank is over half of its capacity. [ABSTRACT FROM AUTHOR]