Search

The partial-response maximum likelihood (PRML) system currently is investigated for practical applications as a modulation/demodulation scheme for digital magnetic recording equipment. This paper proposes a construction of the bit synchronizer by complete digital signal processing. The operational principle is verified by experiment. The proposed bit synchronizer is composed of the decision-feedback digital PLL and the interpolator. The decision-feedback digital PLL receives the data-asynchronous sampled signal sequence as the input, which is the result of sampling by the fixed clock of two samples/bit, and regenerates the clock. The interpolator calculates the signal value at the data point indicated by the phase of the decision-feedback digital PLL output. The result is given to the Viterbi decoder. By applying the proposed scheme, the PRML demodulator from the equalizer to the Viterbi decoder can be realized as a digital signal processing circuit, which operates synchronously with the single fixed master clock. A PRML demodulator is constructed based on the proposed bit synchronizer, and the operational principle is verified by an experiment using a magnetic disk device. The bit-error rate less than 10−6 is obtained for the channel bit rate of 10 Mbps.