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Novel roundoff error bounds for floating-point addition and multiplication are introduced. The error bounds are found to be tighter than conventional error bounds. Tight error bounds are of practical interest as they allow the reduction of intermediate result word lengths, consequently reducing the complexity of dedicated arithmetic hardware. The use of the proposed error bounds is demonstrated by deriving a roundoff error bound for polynomials when used as interpolators.

A new method for conversion from signed digit (SD) to conventional signed-magnitude (SM), radix complement, or diminished radix complement representations is presented. For conversion of an n-digit input, sign detection of n SD numbers called ‘partial’ SD numbers is performed first. Then, the digits of the conventional representation can be generated in parallel. Conversion from radix-2 SD representation to SM representation is presented, as a means of illustrating the method. The proposed method is faster and has a more regular circuit design than the conventional one.

A computationally efficient algorithm for image compression and progressive transmission is presented. A prime-factor discrete cosine transform (DCT) is applied, where the coefficients are computed in three groups and are residue represented by a different bit allocation. A novel lattice vector quantiser is used for the quantisation of each group.