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A new simplified control scheme is proposed for AC–DC electrolytic capacitor-less converters operating in continuous conduction mode (CCM). The proposed method has a single-loop controller responsible for both regulation and power factor correction (PFC). In comparison with the two-loop conventional CCM current mode controller, the proposed scheme does not need a multiplier or extra sensors hence simplifying the control circuitry and its design procedures. Modelling of the closed-loop converter is addressed and experimental results are provided to show the feasibility of the control scheme.

A novel offset-cancelling current-mode sense amplifier (OC-CSA) to improve the sensing speed of embedded flash (eFlash) memory is proposed. To reduce the precharge time related to random address transitions, this OC-CSA adopts a new precharge acceleration scheme. Moreover, by employing offset cancellation, double sensing margin and strong positive feedback techniques, the new OC-CSA can achieve a sensing speed 1.6 × faster than other OC-CSAs. A 130 nm 1 Mb eFlash macro to confirm the high-speed capability of the proposed OC-CSA is fabricated. The experiment results show the new OC-CSA can achieve a read access time of 11 ns at VDD = 1.3 V.

A high-performance current-mode, multi-input winner-take-all maximum circuit is introduced. Owing to low-impedance low-capacitance input nodes involved, the speed of the new circuit is higher than major counterparts. Simulation results show that the new circuit exhibits superior performance compared with well-known rival counterparts in terms of speed, area, dynamic range and power dissipation.

To eliminate the low-frequency oscillation phenomenon in pulse train controlled switching DC–DC converters operating in continuous conduction mode (CCM), a valley current mode pulse train control technique is proposed. The experimental results show that by using the proposed control technique, the low-frequency oscillation in the pulse train (PT) controlled CCM switching DC–DC converter can be eliminated, while the great robustness and excellent transient performance of the traditional PT control technique can be retained.

A 1.5 V high speed low power current sense amplifier for CMOS SRAMs is described. The design is based on the current mode approach and it can be fabricated using a standard CMOS process. The sensing speed is independent of the bit and data line capacitances and no equalisation is needed during the read access. HSPICE simulations have shown that the proposed circuit outperforms the recently reported circuits in terms of speed and average power dissipation.

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements. >

A new nonlinear current-mode controller is presented for DC/DC boost power converters. This controller comprises a linear feedback of the inductor current and a nonlinear feedback of the output voltage. Experimental results demonstrate the effectiveness of the controller.

The idea of shadow filters for modifying the characteristic frequency f0 of second-order filter cells via an external amplifier is generalised to the case of independent control of f0 and bandwidth. This theory is confirmed experimentally on a current-mode biquad.

A small-area digital-to-analogue converter (DAC) in 45 nm SOI CMOS technology is presented that is based on a centrally located, static current-mode DAC, the output current of which is fed to an array of distributed, dynamically-refreshed small-area DACs. Owing to the dynamic operation of the distributed DACs, a single array element can be made as small as 8 × 8 μm. The measured retention time of a single array element with 7-bit resolution is 3 ms at a temperature of 125°C.

A new circuitry is introduced to maintain the constant signal behaviour for rail-to-rail input stages, and is suitable for general mixed-signal ultra-large-scale-integration and system-on-chip applications in contemporary nanoscale CMOS technologies. The constant signal performance is verified by experimental results in a 65 nm standard digital CMOS technology.

A new current-mode CMOS circuit for simultaneous implementation of literal and complementary literal operations is presented. It is shown that the proposed circuit exhibits superior performance compared to its previous counterparts in terms of speed, power dissipation and robustness with much smaller area. These advantages make the circuit a very useful design block for multi-valued logic function realisations.

A new integrated zero-inductor-current detection circuit suitable for step-up DC–DC converters is presented. The detection circuit can correctly detect zero-inductor-current with a novel method. The method helps overcome difficulties in measuring online current from on-resistance of output PMOS switches. With its simplicity and independence from output PMOS switches, this circuit promises wide application in either single-output step-up DC–DC converters or single inductor multiple output (SIMO) step-up DC–DC converters with different control theories, and especially in discontinuous-conduction-mode (DCM) operation.

A new readout circuit involving two-step current-mode background suppression is studied for two-dimensional long wavelength infrared (2D LWIR) focal plane arrays. The simple pixel circuit has a very small skimming error of less than 0.3%, low noise characteristics for an adequate calibration range, and a long integration time of 2 ms.

Presented is a new design method for distributed focal plane image processing, which allows complementary metal oxide semiconductor (CMOS) implementation of two-dimensional, reconfigurable, image-processing kernels at the pixel level.

By exploring the principle of current division, a ratiometric current-steering rational implementation of a rational digital-to-analogue converter (DAC) is proposed. In this implementation, current scaling is achieved through ratios and, as a result, achieve greater independence from actual physical parameters and their associated non-idealities, resulting in the potential for achieving higher accuracy.

A synthesis procedure for generating current-mode low pass filters using a pair of four terminal p-type active current conveyors (CFCCII/sub p/) is presented, and a circuit that realises nth-order low pass current transfer function is given.

The Letter presents a damped integrator for the design of low-voltage (3 V) tunable current-mode filters. The circuit is analysed and the tuning characteristics are discussed.

A low sensitvity current mode filter circuit which realises highpass, bandpass and lowpass responses is proposed.

A new architecture based on summation of currents is proposed for implementing programmable analogue FIR filters. The proposed architecture is more area-efficient compared with architectures based on multiplying digital-to-analogue converters or switched-capacitor techniques. >

A new current-mode CMOS quaternary multiplier circuit is presented. This circuit accepts two 4-valued input currents and a 3-valued CARRY input current and generates a 4-valued SUM output current and a 3-valued CARRY output current. It uses 49 MOS transistors and generates the product in approximately 10 mu s, worst case, in simulations. >

A novel differential current-mode integrator (CMI) for voltage-controllable low frequency continuous-time filters is presented. An example fifth-order lowpass filter using the proposed CMI and on-chip capacitors was implemented in an AMI 1.2 /spl mu/m CMOS process, and it achieved -3 dB cutoff frequencies ranging from 160 Hz to 5.6 kHz, by changing a single control voltage.

The authors have designed a novel high-speed current-mode sense amplifier for dynamic RAMs. The circuitry has no dependency on bit-line capacitances and average input currents. It has been frequently reported that the sensing speed is affected by the degree of input current difference, but the proposed circuitry has shown no considerable changes in its sensing speed when the input current differences are changed.

A general method for designing class AB translinear filters is proposed. The approach is based on the current mode ‘log filters’ recently introduced by Frey, and combines the idea suggested by Seevinck. The class AB filters are shown to consist of current splitters which inherently map the inputs logarithmically, producing the needed inputs to a pair of log filters, whose exponentiated outputs can be subtracted to obtain the final output.

A new method to implement an arbitrary piece-wise-linear characteristic in current mode is presented. Each of the breaking points and each slope is separately controllable. As an example a block that implements an N-shaped piece-wise-linearity has been designed. The N-shaped block operates in the subthreshold region and uses only ten transistors. These characteristics make it especially suitable for large arrays of neuro-fuzzy systems where the number of transistors and power consumption per cell is an important concern. A prototype of this block has been fabricated in a 0.35 μm CMOS technology. The functionality and programmability of this circuit has been verified through experimental results.

A new realisation of a CMOS single resistance current-controlled current mode oscillator using active grounded resistances is described. A prototype has been realised in 0.8 /spl mu/m CMOS technology from AMS. Measurement results confirm oscillation over 10 MHz, low output distortion and wide tuning range.

A versatile current-mode threshold circuit is introduced to implement novel literal and complementary literal gates, which are essential to Postian multi-valued logic implementations. The designed circuits can realise more than one literal operation simultaneously, and exhibit better dynamic behaviour in contrast to previous designs.

Two new current mode single resistance controlled oscillator (CM-SRCO) circuits are presented. Furthermore, it is demonstrated that the recently introduced fully differential current conveyor (FDCCII) is a versatile active element for realising CM-SRCOs. Simulation results with a 0.5 /spl mu/m CMOS realisation of the FDCCII are included, validating the theoretical analysis.

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 mum technology shows a linearity error lower than 0.9% for signal swings up t ...

A current-mode analogue circuit that implements a pseudo-exponential function is proposed. The design of the circuit is based on Taylor's series approximation, using MOS transistors in the saturation region. The advantage of this circuit is that the output current presents a very low temperature coefficient (TC) and is also immune to the body-effect. Simulation and experimental results show that the circuit offers a maximum output range of /spl sim/30 dB, with an error of less than 1 dB and TC=-233 ppm//spl deg/C.

A current-mode full-wave rectifier and current-mode vector summation circuit are presented. They are implemented by utilising the square-law characteristics of MOS transistors in saturation. A two-input vector summation circuit using the proposed full-wave rectifier has been fabricated in a 0.8 /spl mu/m CMOS process. The experimental and simulation results confirm the feasibility of the proposed circuits.

An examination of the technical literature on grounded-capacitor (GC) single resistance controlled oscillators (SRCO) has revealed that no GC-SRCO has so far been published which uses only a single active building block (ABB), only two GCs and provides a current mode (CM) output with simple design equations and unconstrained tuning law. The authors not only introduce such a circuit which uses a single ABB called a 'differential voltage complementary current conveyor' (DVCCC) but also indicate that a DVCCC is a versatile building block for realising SRCOs. The feasibility of the proposed formulation has been verified in PSPICE using a CMOS implementation of the DVCCC.

A current-mode pseudo-exponential circuit is presented based on Taylor's series expansion. It is composed of MOS transistors operating in saturation and its input range can be tuned by adjusting the biased current. The proposed circuit has been verified in 0.8 /spl mu/m CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed pseudo-exponential circuit.

A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided.

A novel self-adaptive current mode sorter is presented. It has a simple structure with a complexity of O(N) and a large dynamic range. No-biasing signal is needed. It performs well even at large input currents. HSPICE simulation shows that this sorter has high precision, high resolution and low power.

A new Kerwin-Huelsman-Newcomb (KHN)-equivalent biquad, operating in the current mode (CM), is proposed. The proposed circuit is derived from the adjoint graph of the signal flow graph corresponding to the classical KHN circuit. The derived circuit is a CM universal filter, which offers all the main advantages of CM circuits as well as those of the classical KHN circuit. The proposed circuit employs three current differencing buffered amplifiers (CDBAs) as active elements. In addition to the three basic filter responses, it also allows the realisation of the notch and allpass responses without requiring any element matching conditions.

A procedure for the systematic realisation of a current-mode FTFN-based inverse filter is proposed. The realisation procedure utilises nullor network analysis and an RC:CR dual transformation. A condition for the correct transformation of a voltage-mode filter to a current-mode inverse filter is also given.

The authors propose a new, fully-integrated universal filter using a current differencing buffered amplifier, a recently introduced active element. It has been shown that the use of the current differencing buffered amplifier in fully-integrated filter design is attractive in that it simplifies the implementation and makes possible the use of a minimum number of grounded capacitors, compared to those using second generation current conveyers and current feedback amplifiers.

A wide-tunable current-mode (CM) gamma corrector for HDTV camera applications is proposed. This gamma corrector provides accurate gamma control over a wide range by simple electrical adjustment of the gain of the weighting amplifier. It has a wide signal bandwidth of >40 MHz. Sufficient for HDTV video signal processing, and can be implemented using a simple integrated circuit with low power consumption.

Current-mode analogue techniques can be employed to realise high-speed, low-power Viterbi decoders. However, signal dependent errors due to charge injection tend to limit the application of these methods to small decoders. A technique is presented for reducing the effects of charge injection on the system performance.

The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 /spl mu/m CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted.

A high CMRR fully-balanced current-mode integrator structure is presented. The proposed structure improves the CMRR at low frequencies by a factor of g/sub m//g/sub o/. Moreover, the structure provides more flexibility to guarantee stability and is significantly less sensitive to process mismatches. The differential and common-mode gains and CMRR at low and high frequencies are analysed as well as verified in simulation.

This comment relates to a previously published letter (see M.T. Abuelma'atti, ibid., vol.32, pp.1457-8, 1996) which presents a cascadable universal current-mode second-order filter using a single four-terminal floating nullor (FTFN) with low active and passive sensitivities. In it, the authors suggest an amended expression for the current-transfer function.

A nonlinear current-mode circuit representation, suitable for a laboratorial realisation, of the Hodgkin and Huxley (HH) nerve axon membrane equations is presented. The representation exploits the inherent properties of the recently proposed 'Bernoulli cell' to calculate the intermediate state variables used in the HH neuron equations.

A novel current amplitude control circuit suitable for current-mode oscillators is proposed. The circuit is a modified version of the well-known Gilbert gain cell. The technique obtains independent control of oscillation amplitude and small-signal current gain. As an example, the amplitude control circuit is applied to a current-mode oscillator. Simulations were carried out using HSPICE with 0.8 /spl mu/m Nortel BiCMOS technology and Motorola RF transistors. Simulated results demonstrate that the nonlinear current gain control circuit behaves in a well defined manner. Low distortion and high frequency oscillations are easily obtained when the circuit is applied to a current-mode oscillator.

A differential voltage clamped current mode delay cell is proposed and a three-stage differential ring oscillator is implemented. Owing to the nature of this current mode, with voltage clamping and robustness against noise, experimental results show that the supply sensitivity is very low at /spl sim/0.1-0.2%/V in the 500-800 MHz range, with its tuning range over 1 decade up to 1.38 GHz.

El pdf del artículo es la versión post-print., A long-term analogue memory based on continuous-time, currentmode algorithmic A/D-D/A converters is presented. It achieves an efficient performance in terms of speed, resolution, power, and area, while incorporating a self-checking ability. Its operation is described and illustrated with experimental results of a CMOS-2.4 μm prototype with 7 bit resolution.

A new configuration for realising cascadable current-mode second-order filters using the single four-terminal floating nullor (FTFN) is presented. The proposed realisations have low active and passive sensitivities and use six passive elements at most.

A novel current-mode biquad using only operational amplifiers (OAs) and multiple current output operational transconductance amplifiers (OTAs) is introduced. The proposed circuit can realise five different biquad transfer functions simultaneously. This circuit enables the circuit characteristics to be electronically tuned. An example is given, together with simulated results by PSPICE.

The author proposes AB class current mode multipliers for use in low power VLSI neural networks and other applications. The analogue AB class building blocks for programmable weight synaptic connections of neuron cells are presented and discussed.

A current-mode sense amplifier, operating at 622 MHz, in a 0.8 µm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing.