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In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM) based memories are widely used in electronic systems and if their contents change due to external reasons, the electronic system can functionally fail. One of the external reasons is the radiation induced soft errors as the SRAM memories are susceptible to radiation effects. Majority of the recently proposed methods use error correction codes (ECC) to mitigate soft errors. Error correction/detection capabilities of such methods are at most 3 bits in a codeword which will be insufficient while number of memory bits affected by a radiation particle is increased, as CMOS process technology shrinks towards around 5 nm. Since memory bits affected by a radiation particle are physically close, adjacent error detection/ correction becomes a hot research topic. In this Letter, Euclidean geometry-low density parity check code, more capable ECC than Hamming code used in recent works, is explored in context of adjacent error detection performance. The results show that proposed method successfully detects up to 14-bit adjacent errors in a 15-bit codeword. As such, this method is suitable where high detection performance is needed. The proposed method is also simplified for efficient hardware implementation while detection performance is not sacrificed. Both methods are compared in terms of resource usage. [ABSTRACT FROM AUTHOR]

An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-toread operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks. [ABSTRACT FROM AUTHOR]