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Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal‐to‐noise‐and‐distortion ratio (SNDR): CMOS switch non‐idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource‐consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out‐of‐sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. [ABSTRACT FROM AUTHOR]

The focus of this Letter is on the development of a new effective approach for the hardware implementation of Volterra filters. The proposed approach is based on exploiting the different significance levels of the branches in a reduced-rank Volterra implementation aiming to reduce the complexity required for implementing each branch. In this Letter, the probability of overflow is used as a metric to define individual word lengths for the fixed-point implementation of each branch. Experimental results corroborate the capability of the proposed approach for obtaining precise implementations with considerable reduction in computational complexity. [ABSTRACT FROM AUTHOR]

A novel transmission system that adaptively compensates for intra- and inter-channel nonlinear distortions while alleviating the computation load is described. It does so by using an optical dispersion compensation at optical nodes and a Volterra-based multi-channel nonlinear equalisation. Simulation results show that 3.8 dB Q-factor improvements are obtained against conventional systems that do not compensate for nonlinear distortions. [ABSTRACT FROM AUTHOR]

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1-2.5 bits (6-15 dB) with 37-101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques. [ABSTRACT FROM AUTHOR]

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10-24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and outof- sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. [ABSTRACT FROM AUTHOR]

The trade-off between transmission performance and hardware implementation in application-specific integrated circuits of digital backpropagation (DBP) in coherent 32 GBd polarisation-division multiplexing 16 quadrature amplitude modulation is analysed. The reach is optimised for different DBP implementations under constraints of 16 and 28 nm complementary metal-oxide-semiconductor (CMOS) technology digital signal processing (DSP) area. [ABSTRACT FROM AUTHOR]

A new linearisation technique for active mixers is introduced to enhance the third-order input intercept point (IIP3). This technique is based on the cancellation of the third-order Volterra kernel in the output current of the transconductance stage by using the interaction between two nonlinear systems. In this scheme, a nonlinear circuit is employed prior to the conventional mixer to improve the total IIP3 by adjusting its second-order Volterra kernel magnitude and phase. Moreover, the added circuit increases the conversion gain of the mixer. The simulation results show that both the IIP3 and the conversion gain simultaneously improve by 13 and 11.4 dB, respectively, compared with the conventional active mixer. [ABSTRACT FROM AUTHOR]

A modified dynamic deviation reduction-based Volterra (MDDRV) model is presented for digital predistortion of power amplifiers. The MDDRV model is a combination of the memory polynomial model and the DDRV model. The effectiveness of the MDDRV model is validated based on experimental results. [ABSTRACT FROM AUTHOR]