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Novel simplified merged processing element (SMPE) architectures to design a low-complexity successive-cancellation (SC) polar decoder are presented. The proposed SMPE architectures reduce the number of sign-magnitude conversions and switch networks, relative to those of the conventional merged processing element. Synthesis results show that the (1024, 512) SC polar decoder using the proposed SMPE architectures significantly decreases hardware complexity and improves technology scaled normalised throughput, as compared to those of the previously reported architectures. [ABSTRACT FROM AUTHOR]

A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders. [ABSTRACT FROM AUTHOR]

A polar coding method to construct a distributed source coding scheme which can achieve any point on the dominant face of the Slepian-Wolf rate region for sources with uniform marginals is proposed. Source encoding and decoding operations are performed using efficient algorithms which makes practical implementation feasible. Simulation results are given to exhibit the performance of the presented method. [ABSTRACT FROM AUTHOR]