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A design of 4/6 intertrack-interference (ITI)-mitigating error correction modulation code for bit-patterned media recording systems is proposed in this Letter. Generally, coding schemes in data storage devices are usually accomplished using a combination of error-correction coding and modulation coding. However, an interesting approach is that the modulation code itself has the capability of correcting errors. Such a modulation code design will reduce the total size and complexity of the data storage devices. In this Letter, the authors design a new 4/6 modulation code, where the code not only mitigates the effect of ITI but also maintains minimum Hamming distance of 2 to build up a trellis structure providing error correction capability of the proposed code. Simulation results show that the proposed design outperforms prior arts. For instance, the performance of the proposed design is better than that of a conventional 4/6 modulation code about 8 dB at a bit error rate of 10−7 under 20% read-head offtrack for the area density of 4 Tb/in2. [ABSTRACT FROM AUTHOR]

To analyse and compare hyperspectral signatures, features extraction and matching are two key issues. In this letter, hyperspectral absorption features and the corresponding matching algorithm are discussed. First, an absorption detection method is applied to catch all necessary spectral absorptions with improved reliability. Then, a weighted Hamming distance is proposed to match the binary absorption‐features. Next, an elastic matching scheme is designed to classify the hyperspectral data. Experiments of classification are carried out on six classes of vegetation from the Salinas data‐set. Results show that the proposed method not only increased the overall classification accuracy to 73.13% from back propagation neural network's 71.86% and support vector machine's 73.06%, but also improved the error distributions among different classes. [ABSTRACT FROM AUTHOR]

A double Hamming distance-based 2D reordering method is proposed for a test set with don'217;t care bits (Xs) to reduce scan-in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering-based methods, the authors'217; method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more Xs are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '217;1-0'217; and '217;0-1'217; logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan-in power consumption but also facilitates code-based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state-of-the-art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run-length coding is improved to 73.76% in average utilising their proposed method. [ABSTRACT FROM AUTHOR]

A double Hamming distance‐based 2D reordering method is proposed for a test set with don't care bits (Xs) to reduce scan‐in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering‐based methods, the authors' method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more Xs are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '1‐0' and '0‐1' logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan‐in power consumption but also facilitates code‐based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state‐of‐the‐art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run‐length coding is improved to 73.76% in average utilising their proposed method. [ABSTRACT FROM AUTHOR]

All test patterns are decoded in the conventional Chase-2 algorithm, but only a few candidate codewords are derived. In this work, a highly efficient Chase-2 decoding algorithm has been proposed, where only the test patterns that can be decoded into distinct candidate codewords are processed. It means that the total number of decoding attempts is reduced from that of the test patterns to that of the candidate codewords, which consequently reduces the complexity, especially in high signal-to-noise ratio (SNR) region. The criterion of the test pattern selection is based on the property of minimum Hamming distance, it can be expected that the proposed algorithm can be applied to all linear block codes without performance degradation compared to the conventional Chase-2 algorithm. [ABSTRACT FROM AUTHOR]

Side channel analysis (SCA) is effective to reveal the key of crypto devices by applying statistical analysis to a number of power traces, thus hardware countermeasure is necessary to protect the crypto circuits. A SCA‐resistance methodology by machine learning trained power compensation module is proposed to compensate the probability of hamming distance (HD) of the intermediate data directly, to make it unable to be distinguished from correct and incorrect sub‐key, thus providing resistance to SCA. The machine learning algorithm is used to find out the best HD redistribution mapping by using neural dynamic programming. Implemented on an AES‐128 encryption algorithm circuit on a Xilinx Spartan‐6 FPGA mounted on a SAKURA‐G board, experimental SCA results show that it can provide more than 200 × measures to disclosure and still has no sign to reveal the advanced encryption standard (AES) sub‐key. In addition, it has low power and area overhead and zero frequency overhead, thus is appropriate for hardware implementation of SCA countermeasure. [ABSTRACT FROM AUTHOR]

Two different subgroups Cn and Ln of symmetric group Sn are first designed and then to construct a family of permutation group codes Pn with code length n, minimum Hamming distance n − 1, cardinalityn(n − 1) and error‐correcting capability n − 2 is composited. [ABSTRACT FROM AUTHOR]

Brute force matching of binary image feature descriptors is conventionally performed using the Hamming distance. The use of alternative metrics is assessed in order to see whether they can produce feature correspondences that yield more accurate homography matrices. Two statistical tests, namely analysis of variance (ANOVA) and McNemar's test were employed for the evaluation. Results show that Jackard‐Needham and Dice metrics can display better performance for some descriptors. Yet, these performance differences were not found to be statistically significant. [ABSTRACT FROM AUTHOR]

To analyse and compare physical unclonable function (PUF) concepts, a set of parameters should be defined to measure performance. The Hamming distance (HD) is a parameter to measure the number of different elements of two strings of the same length. In this reported research, weighted HD is proposed to evaluate and compare the performance of PUFs. The proposed parameter uses weights for calculating similarity measure. The weights can eliminate the effects of noisy responses. The proposed parameter is more efficient and has a low overhead and can be used in identification and authentication applications. [ABSTRACT FROM AUTHOR]

The article offers electronics news briefs including Chinese researchers present a quad-band filtering antenna based on a slotted half-mode substrate has integrated cavity, and the researchers from Vietnam propose a design of 4/6 ITI-mitigating error correction for bit-patterned recording systems.

A masked advanced encryption standard (AES) physical unclonable function (PUF) architecture is proposed for hardware authentication against hybrid side-channel (SCA) and machine-learning attacks (MLAs). The random mismatches of the load capacitance of the masked substitution-boxes in the AES cryptographic circuit induced by the fabrication process are utilised for generating the critical-authentication data against SCAs. Moreover, a mask data is added to the input challenge data to mask the actual input data of the proposed PUF against MLAs. As demonstrated in the results, the masked AES PUF proposed shows a nearly 51.1% uniformity, 50.7% inter- Hamming distance, and 98.1% reliability. Furthermore, if a hybrid SCA/MLA is performed on the proposed PUF by combining the corresponding side-channel leakage with the deep neural network algorithm, the prediction rate of the output responses of the masked AES PUF is only 55.2% after 100,000 number of challenge-to-response pairs are used for training. [ABSTRACT FROM AUTHOR]

Aperiodic Hamming correlation (APHC) is more accurate to measure performances of the frequency hopping (FH) communication systems than periodic Hamming correlation. A class of no-hit-zone FH sequences (FHSs) with respect to APHC which has not yet been studied previously, is studied. A bound on no-hit-zone FHSs with respect to APHC is established. Further, a class of no-hit-zone FHSs with respect to APHC is constructed, which is optimal with respect to the new bound. [ABSTRACT FROM AUTHOR]

Side channel analysis (SCA) is effective to reveal the key of crypto devices by applying statistical analysis to a number of power traces, thus hardware countermeasure is necessary to protect the crypto circuits. A SCA-resistance methodology by machine learning trained power compensation module is proposed to compensate the probability of hamming distance (HD) of the intermediate data directly, to make it unable to be distinguished from correct and incorrect sub-key, thus providing resistance to SCA. The machine learning algorithm is used to find out the best HD redistribution mapping by using neural dynamic programming. Implemented on an AES-128 encryption algorithm circuit on a Xilinx Spartan-6 FPGA mounted on a SAKURA-G board, experimental SCA results show that it can provide more than 200 x measures to disclosure and still has no sign to reveal the advanced encryption standard (AES) sub-key. In addition, it has low power and area overhead and zero frequency overhead, thus is appropriate for hardware implementation of SCA countermeasure. [ABSTRACT FROM AUTHOR]

A class of p-ary (n, k, d) cyclic codes with block length n = p, dimension k = 2 and minimum Hamming distance d = n - k + 1 = p - 1 is introduced, where p denotes a prime. These codes are maximum distance separable repeated-single-root cyclic codes with generator polynomial g(x) = (x-1)p-2. The codebook has size p² and contains a subset S of p(p - 1)codewords having p distinct symbols each. The size of S is maximum for the given parameters and its codewords are useful for applications of coded modulation in power-line communications. [ABSTRACT FROM AUTHOR]

A class of p‐ary (n, k, d) cyclic codes with block length n = p, dimension k = 2 and minimum Hamming distance d = n − k + 1 = p − 1 is introduced, where p denotes a prime. These codes are maximum distance separable repeated‐single‐root cyclic codes with generator polynomial g(x) = (x‒1)p‒2. The codebook has size p2 and contains a subset 𝕊 of p(p ‒ 1)codewords having p distinct symbols each. The size of 𝕊 is maximum for the given parameters and its codewords are useful for applications of coded modulation in power‐line communications. [ABSTRACT FROM AUTHOR]

A condition is proven on the roots of the generator polynomial of a q-ary cyclic code of block length n which guarantees full cyclic order for all nonzero codewords. For such cyclic codes having n = qm – 1, a theorem is proven which allows to partition the set of all nonzero codewords into cyclic equivalence classes of order n. [ABSTRACT FROM AUTHOR]

To analyse and compare physical unclonable function (PUF) concepts, a set of parameters should be defined to measure performance. The Hamming distance (HD) is a parameter to measure the number of different elements of two strings of the same length. In this reported research, weighted HD is proposed to evaluate and compare the performance of PUFs. The proposed parameter uses weights for calculating similarity measure. The weights can eliminate the effects of noisy responses. The proposed parameter is more efficient and has a low overhead and can be used in identification and authentication applications. [ABSTRACT FROM AUTHOR]

A novel bit by bit row/column interleaver (BBRCI) design technique is proposed to significantly increase the minimum Hamming distance (MHD) of block accumulate codes (BACs), making them suitable for optical applications. The proposed BBRCI design method employs a separate row/column interleaver (RCI) for the transmission of each bit position of the outer block code. The numbers of rows of these individual RCIs are properly selected to increase the MHD of the resulting BAC and to reduce the frame size. It is demonstrated that BACs constructed with a BBRCI can be designed to have significantly higher MHD than similar BACs constructed with uniform interleavers (UI) and S type interleavers. Simulations show example BACs constructed with BBRCIs that perform significantly better than those BACs constructed with a UI. [ABSTRACT FROM AUTHOR]

An improved error code correction algorithm for phase-shifted optical quantisation is presented and experimentally demonstrated. The error probabilities for each valid code are calculated and the invalid codes are corrected by using the maximum likelihood estimation algorithm. The experimental result shows that the spur-free dynamic range of the system has an improvement of 2.28 dB compared to the Hamming algorithm in a 10-GSamples/s, 4-bit resolution all-optical analogue-to-digital converter. [ABSTRACT FROM AUTHOR]