Search

This Letter proposes a balanced sampling switch technique for achieving high linearity and a wide temperature range. The proposed technique reduces the VDS of the NMOS sampling switch for reducing the leakage current through the switch during the hold mode. This operation is implemented by a mini capacitive digital‐to‐analogue converter (C‐DAC) that mimics the main C‐DAC used for main SAR conversion. The proposed sampling switch is applied to a 10‐bit, 0.5 V SAR ADC with 5 Msample/s and verified by comprehensive simulation. Compared to the conventional sampling switch without the mini C‐DAC, the proposed switch improves SFDR and SNDR by 27.52 dBc and 11.8 dB, respectively, at the FF corner and 120°C. [ABSTRACT FROM AUTHOR]

Sixteen-chain sequentially rotated fed antenna array on low-temperature cofired ceramic substrate is presented. A 60 GHz broadband circular polarised (CP) stacked rectangular patch antenna is implemented as an element. All the feedlines have the same length which is differentiated from conventional T-junction divider feeder. By this way, several drawbacks of conventional sequential rotated array can be overcome such as phase error occurrence, amplitude mismatch, and axial ratio bandwidth degradation. Moreover, digitally controlled by phase shifters, beamforming performance can be evaluated. The simulated and measured S11 shows broad bandwidth from 57 to 66 GHz. In addition, the radiation patterns show a peak gain of 17.2 dBi and a wide coverage of ±63°. [ABSTRACT FROM AUTHOR]

A high‐voltage extended drain MOS (EDMOS) transistor with a dual work function gate (DWFG) is discussed. This device enhances device performance by modifying the electric field in the channel. For DWFG EDMOS device fabrication, the polycrystalline silicon gates on the source and drain sides are doped by p + and n + ion implantation, respectively. Experimental results from the fabricated DWFG EDMOS devices show improved transconductance (gm), drain conductance (gds) and specific on‐resistance (RON) characteristics without breakdown voltage reduction. [ABSTRACT FROM AUTHOR]

A pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs) is presented. A highly pipelined structure is inevitable in a PACC design to achieve high‐speed performance, which causes a large number of pre‐skewing flip‐flops (F/Fs) and leads clock signals to be a large source of power dissipation. Since the input data do not change every single cycle, clock gating can save power by decreasing the number of unnecessary clock switching in the pre‐skewing F/Fs. Sequential clock gating for pipelined PACCs is proposed. Compared with the conventional pipelined PACCs with and without clock gating, the proposed scheme reduces power dissipation by up to 55.4 and 77.2%, respectively, for the 32‐bit 8‐pipeline‐stage PACCs. [ABSTRACT FROM AUTHOR]

A new analogue circuit design methodology using independently optimised self-cascode (SC) structures is proposed. Based on the concept of the dual-workfunction-gate structures, which are equivalent to SC structures, transconductance and output resistance optimised SC MOSFETs were used in the differential input and output stages, respectively. An operational amplifier (opamp) with the proposed design methodology using standard 0.18 μm CMOS technology was designed to provide better performance. The measured DC gain of the fabricated opamp with independently-optimised SC MOSFETs was approximately 12 dB higher than that of the conventional opamp. [ABSTRACT FROM AUTHOR]