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This letter presents an automatic power‐stage implementation and optimization methodology for fully‐integrated reconfigurable switched‐capacitor (SC) DC‐DC converters with fine‐grained voltage conversion ratios (VCRs). The proposed technique resolves the design challenge of a simultaneous realization of full capacitance utilization, optimal sub‐cell sizing ratio, and implementation complexity reduction. It is based on the proposed partitioning algorithms and attains a significant sub‐cell number reduction, particularly for finer‐grained VCR designs, saving the power‐stage area overhead. With a given set of VCRs and hardware constraints, the proposed methodology can generate a specific power‐stage partitioning solution, including the total number and sizing ratio for the power stage sub‐cells, ensuring an optimal power‐stage conduction loss property under a given on‐chip capacitance area. The proposed methodology is applicable to both linear and binary types of SC converters. Compared with the advanced works, the proposed method realizes the number of sub‐capacitors reduction over 50% under the same VCRs. Meanwhile, over 90% of the sub‐cells can be eliminated for linear‐type SC converters with a VCR range of 10:1–2:1, theoretically. [ABSTRACT FROM AUTHOR]

This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI converter, the proposed techniques tackle the intrinsic hard‐charging property with the MP‐SCI topology, preventing the line‐coupling current through topology operation reconfiguration and power‐switch modulation. The proposed controller also achieves adaptive line‐transition detection and automatic flying‐capacitor voltage balancing, ensuring a fast line regulation feature. Implemented with an MP‐SCI topology for a 9 to 14 V‐input to 5 V‐output conversion, the proposed control techniques provide an output (VOUT) overshoot and undershoot as low as 0.5% of the output DC level under a 3‐V input voltage step. From the simulation, the corresponding output variation reduction can be more than 94% when compared with the existing MP‐SCI operations. Besides, the proposed controller is compatible with a voltage‐mode (VM) V2 pulse‐width modulation (PWM) function, achieving a fast load‐transient recovery in six switching cycles and a VOUT variation of 75 mV at a 5 V DC level under a 0‐to‐3 A load step. The peak conversion efficiency can be as high as 95.5%, and the targeted load current delivery is up to 3 A. [ABSTRACT FROM AUTHOR]

A bipolar junction transistor (BJT)‐based CMOS temperature sensor exploiting the piecewise BJT process spread compensation property of the base recombination current is proposed to reduce the process variations of the base–emitter voltage (Vbe). The weighted combinations of different on‐chip resistors are explored to minimise their associated process spread. Fabricated in standard 0.18‐μm CMOS, the chip prototype occupies an active area of 0.036 mm2 and draws 3 μA from a 1.2 V supply, with a measured maximum inter‐/intra‐die variation in Vbe of <1.5 mV from −40 to 125°C from two batches. Using the measured Vbe, ΔVbe and the first‐batch‐only calibration parameters, the chip prototype demonstrates an untrimmed batch‐to‐batch inaccuracy of ± 1.5°C (3σ) within the same temperature range (24 samples from 2 batches). [ABSTRACT FROM AUTHOR]

A three‐stage amplifier employing embedded capacitor‐multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF‐range capacitive loads (CL) is presented. Unlike the conventional current‐buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left‐half‐plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area‐consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi‐path Gm‐boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three‐stage amplifier measures 1.13 MHz unity‐gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF CL. Stable responses with >50° PM are attained for a 10 × range of CL from 0.15 to 1.5 nF. The achieved figure‐of‐merit accounting for both die area and power compares favourably with the state of the art. [ABSTRACT FROM AUTHOR]