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A Vernier ring‐oscillator‐based time‐to‐digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151mm2. Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22μW at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors. [ABSTRACT FROM AUTHOR]

A novel 9‐bit time–digital‐converter (TDC)‐assisted analogue–digital‐converter (ADC) supporting energy‐efficient high‐speed compressive‐sensing (CS) operation is presented. With a voltage–time‐converter serving as the cross‐domain residue conveyer, the proposed two‐stage self‐timed pipeline ADC architecture hybrids a voltage‐domain comparator‐interleaved successive‐approximation (SAR) ADC front‐end and a time‐domain locally readjusted folding two‐dimensional Vernier TDC back‐end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS‐enabled sub‐Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal‐noise‐distortion‐ratio (SNDR) and a figure‐of‐merit (FOM) of 101 fJ/conversion step. [ABSTRACT FROM AUTHOR]

Three‐dimensional (3D) dynamic random‐access memory (DRAM) with TSVs has been proposed due to continuous demands for low‐power and high‐density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self‐calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double‐data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V. [ABSTRACT FROM AUTHOR]

Oversampled converters based on voltage controlled ring oscillators are an attractive solution because of their digital implementation and simplicity. However, the voltage‐to‐frequency conversion of ring oscillators displays a poor linearity. Replacing the ring oscillator by a pulse frequency modulator (PFM) that provides improved linearity at the expense of feedback and analogue amplification is proposed. Compared to the equivalent continuous time sigma–delta modulators, the PFM may be more tolerant to circuit impairments. In addition, the output data of the proposed architecture is a multibit sequence through the use of a time‐to‐digital converter TDC instead of a Flash quantiser or a multibit digital‐to‐analogue converter. A high dynamic range can be achieved without severe constraints on analogue mismatch or clock jitter. [ABSTRACT FROM AUTHOR]

A time‐to‐digital converter (TDC) for a low‐power, wide‐range all digital phase‐locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 µm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24–1.68 GHz from a 1.2 V supply. [ABSTRACT FROM AUTHOR]