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A novel 0-2 Multi-Stage Noise Shaping (MASH) analogue-to-digital converter (ADC) is proposed. The first stage is implemented using a 4-bit SAR ADC. The second stage uses a voltage controlled oscillator (VCO)-based quantiser (VCOQ). Unlike earlier VCOQs which provide first-order noise shaping, the VCOQ proposed in this Letter achieves second-order noise filtering. To implement this noise shaping, the quantisation noise of the VCOQ is extracted as a pulse-width-modulated signal, and it is fed back to the VCO input using a charge pump circuit. In the proposed scheme, the input signal to the VCO is small. Therefore, the linearity requirement of this block is relaxed. Also, any error related to the charge pump circuitry will be first-order shaped at the output. Simulation results confirm the second-order noise shaping of the output of the ADC, and an excellent (14-bit signal-to-noise and distortion ratio) performance with the over-sampling ratio of 16. [ABSTRACT FROM AUTHOR]

A system-level noise mitigation technique is used to design low-noise single-ended switched-capacitor filters which implement noise shaping. The performance is comparable to that of a fully differential structure, while the complexity, power dissipation and chip area are drastically reduced. [ABSTRACT FROM AUTHOR]

A power efficient noise-coupled ΔΣ analogue-to-digital converter (ADC) is proposed. The new architecture can effectively implement double-noise coupling with simple digital delay cells. For performance improvement, one more input feed-forward path is added to reduce the output swing of an integrator. Zero optimisation technique was also applied to the proposed modulator to increase the signal to quantisation noise ratio (SQNR). A third-order ΔΣ ADC using new configuration was designed and simulated. The results verify the advantages of the proposed architecture. [ABSTRACT FROM AUTHOR]

A discrete-time ΔΣ analogue-to-digital converter utilising a multi-bit successive approximation register quantiser and a segmented digitalto-analogue converter (DAC) is proposed. By adding the delayed DAC output to the modulator input and removing it at the modulator output in the digital domain, the mismatch error is filtered. Thus, a first-order DAC mismatch error shaping is realised. This improves the DAC linearity without introducing an extra delay in the feedback path. Segmenting the DAC and processing the least significant bit and most significant bit segments separately, the dynamic range remains unaffected. [ABSTRACT FROM AUTHOR]

In this Letter, an opamp-free noise shaping successive-approximation register (SAR) ADC is proposed. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantisation noise, comparator thermal noise, DAC thermal noise and settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active element is used, the proposed scheme achieves a higher power efficiency than earlier SAR ADCs. [ABSTRACT FROM AUTHOR]

Anovel complex-pole switched-capacitor lowpass filter topology is presented. The proposed scheme features sharper roll-off in the frequency response and reduced in-band loss compared with a real-pole filter. It provides higher stop-band rejection for the same bandwidth. Hence, the required filter order and chip area are reduced. These improvements are achieved without adding more active blocks to the real-pole filter, and with minimal added complexity. The proposed filter has the same low-output thermal noise level as the real-pole filter. These features, combined with a wide-frequency tuning range, make the filter suitable for high-speed, low-noise, and low-power applications. A fourth-order 200 MS/s filter prototype was designed in 0.18 μm Asahi Kasei Microdevices Corporation CMOS technology. Simulations verify that the average in-band loss is reduced by 3.2 dB compared with the realpole filter. The 3 dB cut-off frequency can be tuned from 470 kHz to 17.5 MHz with 100 dB maximum stop-band rejection. [ABSTRACT FROM AUTHOR]

A highly digital technique is proposed for excess loop delay (ELD) compensation in multi-bit continuous-time ▵ ∑modulators. A digitally controlled reference switching matrix is used to replace the powerhungry signal adder and extra DAC driving the quantiser, which are commonly used in ELD compensation. With the proposed technique, the feedback DAC is embedded in the quantiser and implemented by a few switches. Thus, it allows low-voltage and low-power operation. [ABSTRACT FROM AUTHOR]

A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N - 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N - 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones. [ABSTRACT FROM AUTHOR]

A simple and highly efficient successive-approximation registers (SAR) ADC realisation is proposed. It requires an opamp, a comparator and only three equal-valued capacitors. The proposed scheme is insensitive to the capacitor parasitics, and has a small capacitance spread. With an oversampled scheme, it also allows noise-shaping the remaining quantisation error. It is well-suited for low-frequency instrumentation and measurement applications, and for use in extended-counting ADCs. [ABSTRACT FROM AUTHOR]

A charge compensation technique is proposed for switched capacitor stages with low-gain opamps. It cancels the error charge flow during the operation phase, thus enhancing the accuracy. A capacitive Tnetwork can be employed to implement the resulting large capacitor ratio. A switched-capacitor integrator and a sample-and-hold stage were designed and simulated to verify the proposed technique. [ABSTRACT FROM AUTHOR]

Extended-counting A/D converters are proposed which achieve a high accuracy by performing the conversion in several cycles. During the first cycle, the circuit performs as an incremental ADC, while during the remaining ones it acts as a multi-slope counting converter. With only one opamp and a single-slope ADC, the accuracy is comparable to that of a second-order incremental ADC. A three-step A/D converter using only a single opamp and a two-slope ADC achieves an accuracy comparable to that of a third-order incremental ADC, but with much higher power efficiency. [ABSTRACT FROM AUTHOR]