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A background calibration technique is proposed to correct bit weights in pipelined-successive-approximation-register (SAR) analogue-to-digital converters (ADCs). By splitting the second stage, the input signal interference is mostly removed, thereby greatly enhancing the convergence speed of the algorithm. Besides, the dither signal assists to eliminate mismatch issues between the partially split ADCs, thus relaxing the analogue overheads. According to the simulation, after calibration, the spurious-free-dynamic-range and signal-to-noise-and-distortion-ratio are improved from 53.2 to 88.2 dB and 49.5 to 75.2 dB, respectively. The calibration algorithm converges with about only 600 K samples. [ABSTRACT FROM AUTHOR]

A shaping technique is proposed to remedy the attenuation‐factor error in the split capacitor‐digital‐to‐analogue converter (CDAC) of a successive‐approximation‐register (SAR) ADC. By feeding back the previous quantised value of the least significant bit part to the most significant bit part, the inaccurate attenuation‐factor error caused by mismatches and parasitic components is shaped to high frequency. The in‐band dynamic performance is significantly improved without any calibration. Simulation results show that the proposed attenuation‐factor shaping technique improves the spurious‐free‐dynamic‐range by 10 dB, whereas the number of capacitors increases only 1.2%. [ABSTRACT FROM AUTHOR]

A difference‐equalisation based method is presented to estimate timing skew adaptively in time‐interleaved analogue‐to‐digital converters (ADCs). By digital zero‐crossing detection and calculating the mean of the absolute difference between adjacent sub‐ADC's outputs, the timing mismatch information for each channel can be identified easily. Simulation results demonstrate that the proposed method can estimate timing skew accurately. Furthermore, the proposed method requires far fewer samples to estimation than the previous methods. [ABSTRACT FROM AUTHOR]

High‐efficiency video coding (HEVC) is the next generation standard of video coding. The deblocking filter (DF) constitutes a significant part of the HEVC decoder complexity. A three‐step parallel framework (TPF) is proposed for the H.264/AVC DF, which is also suitable for HEVC except the third step. The third step of the TPF is replaced with a directed acyclic graph‐based order. Experiments show that the proposed method dramatically accelerates more than the state‐of‐the‐art parallel method. [ABSTRACT FROM AUTHOR]