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It is well known that a low level of electrolytes in batteries produces a malfunction or even failure and irreversible damage. There are several kinds of sensors to detect the electrolyte level. Some of them are non-invasive, such as optical sensors of level, while some others are invasive; but both require one sensor per battery. This paper proposes a different approach to detect the low electrolyte level, which neither requires invasive sensors nor one sensor for each battery. The approach is based on the estimation of the internal resistance of an equivalent electrical circuit (EEC) model of the battery. To establish the detection criterion of the low level of electrolytes, a statistical analysis is proposed. To demonstrate the feasibility of this approach to be considered a valid method, multiple experiments were performed. The experiments consisted of determining how the internal resistance is affected at eight different levels of electrolyte at different aging levels of vented lead–acid (VLA) batteries. The results have demonstrated the feasibility of this approach. Hence, this approach has the potential to be used for the reducing of sensors and avoiding invasive methods to determine the low level of electrolytes. [ABSTRACT FROM AUTHOR]

This paper deals with a battery energy storage system (BESS) in only one of its multiple operating modes, that is when the BESS is charging the battery bank and with the focus on the control scheme design for the BESS input stage, which is a three-phase LCL-filter PWM rectifier. The rectifier's main requirements comprise output voltage regulation, power factor control, and low input current harmonic distortion, even in the presence of input voltage variations. Typically, these objectives are modeled by using a dq model with its corresponding two-loop controller architecture, including an outer voltage loop and a current internal loop. This paper outlines an alternative approach to tackle the problem by using not only an input–output map linearization controller, with the aim of a single-loop current control, but also by avoiding the dq modeling. In this case, the voltage is indirectly controlled by computing the current references based on the converter power balance. The mathematical model of the three-phase LCL-filter PWM rectifier is defined based on the delta connection of the filter, which accomplishes the requirements of a 100 kW BESS module. Extensive simulation results are included to confirm the performance of the proposed closed-loop control in practical applications. [ABSTRACT FROM AUTHOR]

This paper presents a control scheme of a wide-area controlled static VAr compensator (WAC-SVC) and its real-time implementation in a hardware-in-the-loop (HIL) simulation scheme with three control objectives: (1) to increase the critical clearing time, (2) to damp the power oscillations, and (3) to minimize the maximum line current. The proposed control scheme considers a correction strategy to compensate the delays up to 200 ms. In addition to this, a generator tripping scheme based on synchrophasor measurements to determine the proximity to the loss of synchronism is proposed. A delay compensation algorithm based on polynomial approximations is also developed. The proposed WAC-SVC is experimentally validated using a Real-Time Digital Simulator platform (RTDS), industrial communication protocols, a commercial device for PMU-based control implementations, and digital relays with PMU capability. The real-time simulation results confirm its effectiveness and feasibility in real industrial applications. Furthermore, practical guidelines to implement this kind of control schemes are provided. [ABSTRACT FROM AUTHOR]