9 results on '"Po‑Hung Lin"'
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2. Overview of 2020 CAD Contest at ICCAD.
3. State retention for power gated design with non-uniform multi-bit retention latches.
4. Overview of 2019 CAD Contest at ICCAD.
5. More effective power-gated circuit optimization with multi-bit retention registers.
6. In-placement clock-tree aware multi-bit flip-flop generation for power optimization.
7. Performance-driven analog placement considering monotonic current paths.
8. A corner stitching compliant B∗-tree representation and its applications to analog placement.
9. Post-placement power optimization with multi-bit flip-flops.
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