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Circuits possess an irregular representation. Hence, their data structure (e.g., gate-level netlists) necessitate the encoding into fixed formats like vectors. For machine learning-based tasks, such vectors are the expected format. In contrast, brain-inspired hyperdimensional computing (HDC) can process irregular data structures with its unique encoding algebra. This work is the first to propose HDC for optimized circuit encoding and learning. One advantage of HDC over conventional deep learning algorithms is that it does not require extensive training to encode a gate-level netlist into a hypervector. Furthermore, with HDC-based circuit encoding, the similarity between circuits is efficiently computed as the similarity between their hypervectors, enabling a wide range of applications, such as circuit recognition, verification, and optimization. We introduce CircuitHD, a versatile HDC-based framework for circuit encoding and learning, featuring three encoding methods, each with specific advantages. We demonstrate its effectiveness in two applications: circuit recognition and the detection of hardware intellectual property (IP) piracy, using ITC-99 and ISCAS-85 benchmarks. In circuit recognition, CircuitHD maintains a 97% accuracy, even when the designs are obfuscated using logic locking. It detects IP piracy across diverse scenarios, achieving a 97.8% precision, outperforming a state-of-the-art graph neural network approach, with a precision of merely 81%.

The recent renaissance in machine learning is requesting computing power at an ever-increasing rate. In order to meet this demand, tensor processing units (TPU) are becoming popular because they hold the promise to be more efficient in terms of power usage as well as throughput compared to GPUs. This is achieved by integrating a huge number of matrix-multiply units (MMU) to perform a massive amount of parallel multiply-accumulate operations. However, this causes excessive localized hot-spots. Elevated on-chip temperatures jeopardize reliability and significantly reduce the lifetime of semiconductor devices by accelerating aging defects. Therefore, it is vital to obtain accurate thermal maps of the TPU die at the design time to ensure reliability requirements during the run-time. Due to the high power density, traditional forced air convection cooling is often insufficient. Hence, liquid cooling may seem promising, but it requires substantial maintenance effort. To overcome this challenge, novel cooling concepts need to be explored. Recent advances in thermoelectric coolers (TEC), more specifically ultra thin-film superlattice thermoelectric (TE) devices, have opened new doors to combat this obstacle. To this end, finite-element (FEM) simulations enable designers to find tradeoffs between temperature and cooling cost. However, such multi-physics simulations are extremely time-consuming, which prevents designers from exploring the available design-space. In this work, we demonstrate a neural network (NN) model that captures the effects of a superlattice TEC device mounted on top of a TPU die. The additional required cooling cost is also estimated. The commercial multi-physics tool ANSYS is employed in order to obtain high resolution data towards training the NN model. Our NN model allows to speed up the design-space exploration considerably, reducing the time required to generate a single thermal map from, on average, 45 min in ANSYS to merely 70 ms with an average prediction error of 0.26°C. Our model covers a wide range of design parameters, such as convection film coefficient, power density and superlattice TEC cooling intensity. Open Source: https://github.com/ML-CAD/TPU-Thermal-Map-Prediction.git Our framework including the generated thermal image dataset and the trained neural network models are publicly available under the above link.

Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guard bands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guard band and performance loss from lowering the voltage.

This is the first work to investigate the impact that Negative Capacitance Field-Effect Transistor (NCFET) brings on the efficiency and accuracy of future Neural Networks (NN). NCFET is at the forefront of emerging technologies, especially after it has become compatible with the existing fabrication process of CMOS. Neural Network inference accelerators are becoming ubiquitous in modern SoCs and there is an ever-increasing demand for tighter and tighter throughput constraints and lower energy consumption. To explore the benefits that NCFET brings to NN inference regarding frequency, energy, and accuracy, we investigate different configurations of the multiply-add (MADD) circuit, which is the core computational unit in any NN accelerator. We demonstrate that, compared to the baseline 7nm FinFET technology, its negative capacitance counterpart reduces the energy by 55%, without any frequency reduction. In addition, it enables leveraging higher computational precision, which results to a considerable improvement in the inference accuracy. Importantly, the achieved accuracy improvement comes also together with a significant energy reduction and without any loss in frequency.

Monolithic 3D (M3D) integration reduces the wire length, which eventually improves energy efficiency and performance compared to 2D integration. However, 3D integration inevitably causes higher on-chip temperature compared to 2D integration due to the increased power density as well as worse heat dissipation. The high on-chip temperature may offset the benefits of the M3D microprocessors due to the following reasons: 1) high on-chip temperature increases leakage power, which degrades energy efficiency. 2) the actual clock frequency is limited at run-time by frequent dynamic thermal management (DTM) invocations. In this paper, for the first time, we explore the thermal feasibility (whether it is possible to achieve high energy efficiency and performance without exceeding threshold temperature) of the M3D microprocessors depending on cooling solutions. For the thermal feasibility study, we construct an integrated framework to investigate the thermal behaviors and thermal feasibility of different types of microprocessors (M3D, 2D, and through-silicon-via based 3D (TSV-3D)) with different cooling solutions. Our thermal-aware evaluation results show that the best configuration of the M3D microprocessors reduces average energy consumption by 27.6% compared to the 2D microprocessor at an iso-frequency (4.0GHz). In addition, at the highest clock frequencies satisfying both design and thermal constraints, the best configuration of the M3D microprocessors improves average system performance by 25.1% and 26.0% compared to the 2D and TSV-3D microprocessors, respectively.

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TEC-based cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

Leveraging the inherent error tolerance of a vast number of application domains that are rapidly growing, approximate computing arises as a design alternative to improve the efficiency of our computing systems by trading accuracy for energy savings. However, the requirement for computational accuracy is not fixed. Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime. In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime. The generated circuits feature varying accuracy levels, supporting also accurate execution. Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average under a pessimistic scenario that assumes full accuracy requirement in the 33% of the runtime. To demonstrate further the efficiency of our framework, we considered two state-of-the-art technology libraries which are a 7nm conventional FinFET and an emerging technology that boosts performance at a high cost of increased dynamic power.

This paper reports a novel approach that uses transistor aging in an integrated circuit (IC) to detect hardware Trojans. When a transistor is aged, it results in delays along several paths of the IC. This increase in delay results in timing violations that reveal as timing errors at the output of the IC during its operation. We present experiments using aging-aware standard cell libraries to illustrate the usefulness of the technique in detecting hardware Trojans. Combining IC aging with over-clocking produces a pattern of bit errors at the IC output by the induced timing violations. We use machine learning to learn the bit error distribution at the output of a clean IC. We differentiate the divergence in the pattern of bit errors because of a Trojan in the IC from this baseline distribution. We simulate the golden IC and show robustness to IC-to-IC manufacturing variations. The approach is effective and can detect a Trojan even if we place it far off the critical paths. Results on benchmarks from the Trust-hub show a detection accuracy of ≥ 99%.

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore's law, which is approaching its end, but also for reviving Dennard's scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.