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The widespread use of smartphones has brought convenience and connectivity to the fingertips of the masses. As a result, this has paved the way for potential security vulnerabilities concerning sensitive data, particularly by exploiting side-channel attacks. When typing on a smartphone’s keyboard, its vibrations can be misused to discern the entered characters, thus facilitating side-channel attacks. These smartphone hardware sensors can capture such information while users input sensitive data like personal details, names, email addresses, age, bank details and passwords. This study presents a novel Graph Neural Network (GNN) approach to predict side-channel attacks on smartphone keyboards; different GNN architectures were used, including GNN, DeepGraphNet, Gradient Boosting (GB)+DeepGraphNet, Extreme Gradient Boosting (XGB)+DeepGraphNet and K-Nearest Neighbor (KNN)+DeepGraphNet. The proposed approach detects the side channel attack using vibrations produced while typing on the smartphone soft keyboard. The data was collected from three smartphone sensors, an accelerometer, gyroscope, and magnetometer, and evaluated this data using common evaluation measures such as accuracy, precision, recall, F1-score, ROC curves, confusion matrix and accuracy and loss curves. This study demonstrated that GNN architectures can effectively capture complex relationships in data, making them well-suited for analyzing patterns in smartphone sensor data. Likewise, this research aims to fill a crucial gap by enhancing data privacy in the information entered through smartphone keyboards, shielding it from side-channel attacks by providing an accuracy of 98.26%. Subsequently, the primary objective of this study is to assess the effectiveness of GNN architectures in this precise context. Similarly, the GNN model exhibits compelling performance, achieving accuracy, precision, recall, and f1 score metrics that showcase the model’s effectiveness, with the highest values of 0.98, 0.98, 0.98, and 0.98, respectively. Significantly, the metrics mentioned in the study outperform those documented in the previous literature. Overall, the study contributes to the detection of side-channel smartphone attacks, which advances secure data practices.INDEX TERMS Graph neural networks (GNN), keystroke inference, motion sensors, machine learning, smartphone security, side-channel attacks.

The continuing proliferation of Cyber Physical Systems (CPSs), those that integrate electronic control circuitry with a mechanical system allowing software commands to affect the physical world, while allowing for new efficiencies and convenience, also facilitates new security risks. While the cyber-domain components of a CPS control the behavior of the physical-domain components, attacks on either the physical-domain or cyber-domain can be used to control or subvert the CPS in ways that may cause serious harm or even loss of life. Unfortunately, most research in CPS attack detection has focused solely on monitoring the cyber domain for malicious software activity, and the few works that do monitor the physical domain neglect or independently monitor the cyber domain. With that in mind, this paper proposes a method of jointly monitoring both domains (cyber and physical) of a CPS, verifying not only that software commands are faithfully executed by the cyber-components of the CPS, but also that the physical-domain behavior of the CPS corresponds to those commands. We demonstrate the effectiveness of this approach through experiments using a medical CPS device subjected to both cyber and physical attacks. We show that different analog side channels (EM and acoustic in our experiments) are similarly effective for such monitoring and attack detection. We also show that, while some attacks can be detected through physical-domain monitoring alone or through cyber-domain monitoring alone, our joint monitoring of both domains allows for the detection of additional attacks that cannot be detected by monitoring only one of the domains, resulting in >99% attack detection accuracy measured over 1,000 instances of CPS activity.

Substitution boxes (S-Boxes) are essential elements of modern block ciphers, serving as non-linear characteristics that enhance the resistance of these ciphers against cryptanalysis. This research presents a new approach for constructing lightweight S-Boxes that possess strong cryptographic characteristics by combining an enhanced logistic map and an enhanced sine map. The proposed novel algorithm has optimized multiple parameters according to the security threshold set. This study has conducted the most comprehensive evaluation of criteria for S-Boxes to date. The analysis results of the generated $4\times 4$ and $5\times 5$ S-Boxes have achieved optimal criteria in terms of the Strict Avalanche Criterion (SAC) and the Bit Independence Criterion (BIC) that no previous S-Boxes have achieved. Furthermore, parameters related to side-channel attack resistance have been optimized in the design stage of S-Boxes. The constructed S-Boxes with high security can be applied to replace S-Boxes of the same size in existing algorithms or to develop lightweight block cipher algorithms. This research has made a significant contribution to the construction of S-Boxes.

Correlation power analysis (CPA) is a classical method in side-channel attacks. Based on the power consumption model, the correlation between the power consumption of cryptographic devices and the assumed intermediate value is analyzed to recover the key. Theoretically, only a few power traces are required to recover the key when the noise hypothesis is known. However, in the high-frequency and high-noise environment, the completion of CPA requires more power traces, and the computational complexity also increases. Therefore, this paper proposes a fault probability correlation analysis method based on secondary filtering (2F-FPCA), which selects the fault probability traces according to the Hamming Weight of the intermediate value and reduces the number of sampling points by selecting points of interest. This method does not need to access ciphertext and is little affected by noise. Moreover, it can recover the key with fewer fault probability traces and lower computational complexity, improving the attack efficiency of CPA. In this paper, 2F-FPCAs are carried out based on the AES-128 algorithm of the Micro Controller Unit (MCU). The key can be recovered successfully using 10 fault probability traces, and the computational complexity is reduced by 104 times.

Signature can be used to verify the integrity of both a message and the identity of a signer, whereas encryption can be used to ensure the confidentiality of a message. In the past, cryptography researchers have studied and proposed numerous certificateless signcryption (CLSC) schemes to combine the benefits of both signature and encryption. However, these schemes may not be robust enough to withstand side-channel attacks. Through such attacks, an attacker can constantly retrieve a portion of a private key of the system, and could eventually recover the entire private key. Leakage-resilient certificateless signcryption (LR-CLSC) can ensure its security when the attacker launches such attacks. As far as we know, the existing LR-CLSC schemes can only guarantee the security under a bounded leakage model, where the portion of the private key that an attacker can obtain through side-channel attacks is limited. In this paper, we propose the $first$ LR-CLSC scheme under a continual leakage model. Also, we demonstrate the proposed scheme is secure for the existential unforgeability and the ciphertexts indistinguishability against attackers with side-channel attacking abilities.

Key encapsulation schemes in public key system (PKS) can be used to protect sensitive or private data. Unlike traditional PKS and identity-based PKS, certificate-based PKS (CB-PKS) not only avoids the establishment of complex public key infrastructures, but also does not encounter the key escrow problem. Anonymous multi-receiver certificate-based encryption (AMR-CBE) or anonymous multi-receiver certificate-based key encapsulation (AMR-CB-KE) scheme enables a sender to use multiple receivers’ public keys to perform one-time encryption process for a message and send the encrypted ciphertext to these receivers, while these receivers do not know the other receiver’s identity. However, the existing AMR-CBE and AMR-CB-KE schemes cannot resist side-channel attacks. Attackers with the ability of such attacks can continuously obtain part (several bits) of the secret keys and then calculate the complete secret keys. In such a case, such attacks make a cryptographic scheme (including AMR-CBE and AMR-CB-KE schemes) insecure. Leakage-resilient cryptography is an important research topic to resist side-channel attacks. In this paper, we propose the first leakage-resilient anonymous multi-receiver certificate-based key encapsulation (LR-AMR-CB-KE) scheme. Based on the discrete logarithm and hash function assumptions, we demonstrate the scheme has the indistinguishability of two ciphertexts against chosen ciphertext attacks (IND-CCA) and the anonymous indistinguishability of two identities against chosen ciphertext attacks (ANON-IND-CCA) for two types of attackers in CB-PKS settings.

Cloud providers are increasingly exposed to malicious actors through transient attacks, such as Spectre and Meltdown. The cache hierarchy is the main target to build the required side-channels to leak data. Randomized caches can be employed to provide security but often rely on cryptographic primitives to deter side-channel attacks. These increase the access latency and deteriorates the system performance. This paper shows that randomized caches do not have to increase the cache access latency, and that their security does not have to rely on a cryptographic hash function or block-cipher. Herein, CoDi $\$ $ is proposed, a randomized last level cache that achieves security by tying the local and global states. Security is achieved through a higher miss energy consumption and occupied area, instead of penalizing performance. CoDi $\$ $ is able to evict any cached address by allowing addresses to be displaced in two levels of freedom, through hopscotch (local state) and cuckoo hashing (global state), without increasing the hit latency. Through these displacements, paths can be built to the eviction address. The security of CoDi $\$ $ relies on the hardness to control all possible displacement paths when a miss occurs, which requires control over the local and global states of the cache simultaneously. Confusion is generated when evicting an address, as there are many possible cache states that could result from this eviction. Also, for each executed eviction, multiple addresses in the cache are non-deterministically displaced, providing diffusion. Moreover, experimental analysis for a 48-bit secure CoDi $\$ $ , using SPEC, NPB, and Polybench benchmarks, shows improvements in the number of instructions per cycle and up to 5% in misses, when compared to two state-of-the-art randomized caches.

BREACH is a side-channel attack to HTTPS that allows an attacker to obtain victims’ credentials under certain conditions. An attacker with a privileged position on the network can guess character by character a secret session key just by analyzing the size of the responses returned by the server over HTTPS and encrypted. Heal the Breach (HTB) is the proposed technique to mitigate BREACH attack by randomly changing the size of server responses through a modified gzip library. The attacker needs a precision of one byte in the size of the responses to be able to determine if a guess character is part of the secret token. Since the modified gzip library introduces randomness in the size of the response, BREACH becomes ineffective. The only way to circumvent this protection is to make several requests and compute the average size of the response, which minimizes the random effect. Mathematical and experimental results show that, for a random variation of the size from 1 to 10 bytes, an attacker needs to analyze 500 times more packages to obtain enough accuracy and surpass this mitigation. However, if the number of requests increases it is easier to isolate and block the attack using standard Intrusion Detection Systems (IDS). Compared to other mitigations, the approach presented in this paper is very effective, easy to implement for all websites hosted in the server, and produces a negligible increase in normal traffic.

A multi-recipient signcryption (MRSC) scheme possesses the functionalities of both multi-recipient public-key encryption and digital signature to ensure both integrity and confidentiality of transmitted messages. Moreover, an anonymous MRSC (AMRSC) scheme retains the functionalities of an MRSC scheme while offering privacy-preserving, namely, a recipient’s identity or public key being hidden to other recipients. In the past, numerous MRSC and AMRSC schemes based on various public-key cryptographies (i.e., public key infrastructure (PKI)-based, identity (ID)-based and certificateless (CL)) were proposed. Recently, an attacker can realize side-channel attacks to acquire partial bits of private keys participated in cryptographic computations. However, up to date, no MRSC or AMRSC scheme can resist side-channel attacks so that these schemes might suffer from such attacks and could be broken. To resist such attacks under a continual leakage model, we propose the $first$ PKI-based leakage-resilient AMRSC (PKI-LR-AMRSC) scheme in this paper. In the proposed scheme, an attacker is permitted to continually acquire partial bits of private keys partook in computations of the PKI-LR-AMRSC scheme, and formal security proofs are given to show that the proposed scheme still retains the original security of AMRSC schemes. As compared with the relevant AMRSC schemes, our PKI-LR-AMRSC scheme not only resists side-channel attacks but also reduces the cost of executing the multi-signcryption and unsigncryption algorithms. In particular, the point is that the computational complexities of our scheme respectively require only $O(t)$ and $O(1)$ in executing the Multi-signcryption algorithm and the Unsigncryption algorithm, where $t$ is the number of recipients.

The differential deep learning analysis proposed by Timon is the first non-profiled side-channel attack technique that uses deep learning. The technique recovers the secret key using the phenomenon of deep learning metrics. However, the proposed technique made it difficult to observe the results from the intermediate process, while the neural network had to be retrained repeatedly, as the cost of learning increased with key size. In this paper, we propose three methods to solve the aforementioned problems and any challenges resulting from solving these problems. First, we propose a modified algorithm that allows the monitoring of the metrics in the intermediate process. Second, we propose a parallel neural network architecture and algorithm that works by training a single network, with no need to re-train the same model repeatedly. Attacks were performed faster with the proposed algorithm than with the previous algorithm. Finally, we propose a novel architecture that uses shared layers to solve memory problems in parallel architecture and also helps achieve better performance. We validated the performance of our methods by presenting the results of non-profiled attacks on the benchmark database ASCAD and for a custom dataset on power consumption collected from ChipWhisperer-Lite. On the ASCAD database, our shared layers method was up to 134 times more efficient than the previous method.

Deep Learning Side-Channel Attacks (DLSCAs) have become a realistic threat to implementations of cryptographic algorithms, such as Advanced Encryption Standard (AES). By utilizing deep-learning models to analyze side-channel measurements, the attacker is able to derive the secret key of the cryptographic algorithm. However, when traces have multiple leakage intervals for a specific attack point, the majority of existing works train neural networks on these traces directly, without a appropriate preprocess step for each leakage interval. This degenerates the quality of profiling traces due to the noise and non-primary components. In this paper, we first divide the multi-leaky traces into leakage intervals and train models on different intervals separately. Afterwards, we concatenate these neural networks to build the final network, which is called multi-input model. We test the proposed multi-input model on traces captured from STM32F3 microcontroller implementations of AES-128 and show a 2-fold improvement over the previous single-input attacks.

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

In recent years, deep learning-based side-channel attacks have established their position as mainstream. However, most deep learning techniques for cryptanalysis mainly focused on classifying side-channel information in a profiled scenario where attackers can obtain a label of training data. In this paper, we introduce a novel approach with deep learning for improving side-channel attacks, especially in a non-profiling scenario. We also propose a new principle of training that trains an autoencoder through the noise from real data using noise-reduced labels. It notably diminishes the noise in measurements by modifying the autoencoder framework to the signal preprocessing. We present convincing comparisons on our custom dataset, captured from ChipWhisperer-Lite board, that demonstrate our approach outperforms conventional preprocessing methods such as principal component analysis and linear discriminant analysis. Furthermore, we apply the proposed methodology to realign de-synchronized traces that applied hiding countermeasures, and we experimentally validate the performance of the proposal. Finally, we experimentally show that we can improve the performance of higher-order side-channel attacks by using the proposed technique with domain knowledge for masking countermeasures.

This paper presents UCloD, a novel random clock delay-based robust and scalable countermeasure against recently discovered remote power analysis (RPA) attacks. UCloD deploys very small clock delays (in the picosecond range) generated using the tapped delays lines (TDLs) to mitigate RPA attacks. UCloD provides the most robust countermeasures demonstrated thus far against RPA attacks. RPA attacks use delay sensors, such as Time to Digital Converters (TDC) or Ring Oscillators (ROs) to measure voltage fluctuations occurring in power delivery networks (PDNs) of Field Programmable Gate Arrays (FPGAs). These voltage fluctuations reveal secret information, such as secret keys of cryptographic circuits. The only countermeasure proposed thus far activates ROs to consume significant power and has managed to secure Advanced Encryption Standard (AES) circuits for up to 300,000 encryptions. Using TDLs available in FPGAs, UCloD randomly varies the clock to the cryptographic circuits under attack to induce noise in the adversary’s delay sensor(s). We demonstrate correlation power analysis (referred to as CPA) attack resistance of UCloD AES implementations for up to one million encryptions. Compared to an unprotected AES circuit, UCloD implementations have minimal overheads (0.2% Slice LUT overhead and 4.8% Slice register overhead for Xilinx implementations and 0.5% LogicCells overhead for Lattice Semiconductor implementations).

Vehicular ad hoc networks (VANETs) have become increasingly common in the past decades and provides essential and efficient communication for vehicles within intelligent transportation systems. Securing the VANETs wireless communication channel is one of the principal challenges in VANETs since existing security schemes are still vulnerable to security and privacy issues and have substantial computational and communicational overheads. To overcome these issues, this paper focuses on enhancing an authentication scheme based on conditional privacy-preserving and improving its performance efficiency. This paper reviews the security vulnerabilities of the existing schemes. It also proposes enhancements to the identity-based conditional privacy-preserving authentication scheme to secure and improve the efficiency of VANETs communications. The proposed scheme not only satisfies the security and privacy requirements but also has been proven secure under the random oracle model. Finally, the performance evaluation shows that the proposed scheme is more efficient computationally and communicational than the existing schemes in signing and verifying VANETs messages.

Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC’s resistance against DL-SCA attacks.

As machine learning (ML) technologies and applications are rapidly changing many computing domains, security issues associated with ML are also emerging. In the domain of systems security, many endeavors have been made to ensure ML model and data confidentiality. ML computations are often inevitably performed in untrusted environments and entail complex multi-party security requirements. Hence, researchers have leveraged the Trusted Execution Environments (TEEs) to build confidential ML computation systems. We conduct a systematic and comprehensive survey by classifying attack vectors and mitigation in confidential ML computation in untrusted environments, analyzing the complex security requirements in multi-party scenarios, and summarizing engineering challenges in confidential ML implementation. Lastly, we suggest future research directions based on our study.

NTRUEncrypt is a public key cryptosystem based on hard problems over lattices. The dominant operation in NTRUEncrypt is convolution, i.e., multiplication over a quotient ring of polynomials. Based on the fact that a convolution has a highly regular structure, Lee et al. proposed the sliding window method for fast convolution of binary polynomials in 2013, which was then extended to ternary polynomials for ideal lattices by Akleylek, Alkim, and Tok in 2016. These sliding window methods reduce the cost of a convolution operation using look-up tables that store partial computation results related to repeated coefficient patterns. In this paper, we propose a signed sliding window method with side-channel resistance for NTRUEncrypt. The proposed method considers both positive and negative nonzero coefficients when constructing look-up tables. The new method not only accelerates convolution but also enables the application of power analysis countermeasures effectively. According to the experimental results, the constant-time implementation of the proposed method with timing and power analysis countermeasures accelerates the previously developed secure convolution method by up to 20%.

Advanced collision-based single trace attacks which can be applied on simple power analysis resistant scalar multiplications become virtual threat on elliptic curve cryptosystems recently as their practical experimental results are increasingly reported in the literature. Since such attacks are based on detecting collisions of data dependent leakage caused by underlying long integer multiplications, so-called global shuffling countermeasure which breaks such collision correlation by independently randomizing the execution order of unit operations such as single precision multiplication and carry propagation, is considered as promising countermeasure if theoretical randomness of shuffling order is guaranteed. In this paper, we firstly analyze the practical security of the global shuffling long integer multiplications by exhibiting a combined single trace attack on software implementations on an ARM Cortex-M4 microcontroller. Our combined attack consists of a simple power analysis for revealing random permutation vectors which enables later collision-based single trace attack. First we demonstrate how to reveal random permutation vectors for carry propagation process of whole global shuffling long integer multiplications within a single power trace by simple power analysis accompanied with straightforward substitution of power consumption samples. Then we perform collision-based single trace attacks after rearranging the order of subtraces for unit carry propagations based on revealed permutation vectors. Since the vulnerability to simple power analysis is originated from the if-statement for selection of proper entries of the permutation vectors, we propose a novel countermeasure which eliminates such selection with simple addition and modulus operation and also demonstrate practical result achieving regularity in power trace patterns.

Certificateless public-key cryptography has conquered both the certificate management problem in the traditional public-key cryptography and the key escrow problem in the ID-based public-key cryptography. Certificateless authenticated key exchange (CLAKE) protocol is an important primitive of the certificateless public-key cryptography. A CLAKE protocol is employed to provide both mutual authentication and establishing a session key between two participators. Indeed, all conventional public-key cryptographies have encountered a new kind of attack, named “side-channel attacks”. Fortunately, leakage-resilient cryptography is a flexible approach to withstand such attacks. However, the design of leakage-resilient CLAKE (LR-CLAKE) protocols is not studied. In the article, by extending the well-known extended-Canetti-Krawczyk (eCK) model, we present the security notions (adversary model) of LR-CLAKE protocols, called continual-leakage-resilient eCK (CLReCK) model. The first LR-CLAKE protocol withstanding side-channel attacks is proposed. By employing the proof technique of the generic bilinear group (GBG) model, we formally prove the security of our protocol in the CLReCK model.

Recent work has shown that the timing behavior of a real-time system can be utilized by attackers for various adverse purposes via schedule-based timing side-channel attacks. An important assumption in this type of attacks is the prior knowledge of attackers about the task parameter information, including the number of tasks in the system and the period and execution time of each task. The attackers can use such information, together with the execution sequence of the task system, to reconstruct the exact schedule of the tasks and perform various subsequent attacks. In this paper, we show that the schedule-based timing side channel attacks can actually be performed even without knowing the task parameter information in prior. We develop methods to infer the number of tasks in the system and the period and execution time of each task directly from the execution sequence. This removes the task parameter prior knowledge requirement of the attackers and shows greater threats of the schedule-based timing side channel attacks. Both simulation experiments with synthetic task sets and a Zedboard-based evaluation with control system for a 3DOF helicopter are conducted to evaluate the proposed task parameter analysis method.

Deep learning-based side channel attacks are burgeoning due to their better efficiency and performance, suppressing the traditional side-channel analysis. To launch the successful attack on a particular public key cryptographic (PKC) algorithm, a large number of samples per trace might need to be acquired to capture all the minor useful details from the leakage information, which increases the number of features per instance. The decreased instance-feature ratio increases the computational complexity of the deep learning-based attacks, limiting the attack efficiency. Moreover, data class imbalance can be a hindrance in accurate model training, leading to an accuracy paradox. We propose an efficient Convolutional Neural Network (CNN) based approach in which the dimensionality of the large leakage dataset is reduced, and then the data is processed using the proposed CNN based model. In the proposed model, the optimal number of convolutional blocks is used to build powerful features extractors within the cost limit. We have also analyzed and presented the impact of using the Synthetic Minority Over-sampling Technique (SMOTE) on the proposed model performance. We propose that a data-balancing step should be mandatory for analysis in the side channel attack scenario. We have also provided a performance-based comparative analysis between proposed and existing deep learning models for unprotected and protected Elliptic curve (ECC) Montgomery Power ladder implementations. The reduced network complexity, together with an improved attack efficiency, promote the proposed approach to be effectively used for side-channel attacks.

The aim of this paper is to describe the characteristics of a toolbox developed to carry out a side-channel analysis of cryptosystems implemented in physical devices. The toolbox, called RamDPA and developed in C++, is flexible and modular and has been initially designed to carry out differential power analysis attacks. Different modules are used to enter text, keys, and hypothetical values related to the cryptographic algorithm under analysis, to control the digital oscilloscope in charge of the acquisition of power consumption traces, and to carry out the statistical operations to get the unknown key. An analysis of the different options to program the modules has been performed in order to optimize the toolbox in terms of memory consumption and execution time. Usually, the optimization of side-channel attacks comes from the selection of points-of-interest and re-sampling. Instead of that approach, the proposed toolbox optimizes DPA attacks from caching strategy and multithreading. Results are presented by applying RamDPA to extract an AES-128 key with the traces provided by the CHES2016 capture The Flag challenge.

Certificate-based cryptography is an attractive public-key setting, and it not only simplifies certificate management in the traditional public-key cryptography but also eliminates the key escrow problem inherent in the identity-based cryptography. Recently, leakage-resilient cryptography resistant to side-channel attacks has received significant attention from cryptographic researchers. By side-channel attacks, adversaries could obtain partial information of secret and private keys involved in cryptographic algorithms by perceiving execution time or energy consumptions of each algorithm invocation. The certificate-based signature (CBS) is a class of important public-key signature. Up to date, there exists no leakage-resilient CBS (LR-CBS) scheme resistant to side-channel attacks. In this paper, the first LR-CBS scheme is proposed and it possesses overall unbounded leakage property, namely, it permits adversaries to continuously obtain partial information of secret or private keys involved in the associated algorithm invocations. The security analysis is given to prove that the proposed LR-CBS scheme is existential unforgeability against adaptive chosen-message attacks for adversaries in the generic bilinear group model.

We analyze the security of RSA prime generation implemented on embedded devices by a practical power analysis attack. Unlike previous differential power analysis-based attack on primality tests of RSA prime generation exploiting the deterministic relationship among multiple prime candidates manipulated by consecutive primality tests, we propose a collision-based power analysis attack on the Miller-Rabin test for a single prime candidate which can recover the secret prime with a single attempt by exploiting collision characteristics of simple power analysis resistant modular exponentiation algorithms. Hence, our attack does not require the incremental prime search assumption and is applicable when countermeasures against previous attacks are deployed since it also does not require the assumption of trial divisions with small primes on prime candidates. For a realistic setting, where five 512-bit modular exponentiations are operated on an ARM Cortex-M4 microcontroller as recommended by FIPS 186-4 standard, we successfully recover the secret exponent to an extent that a feasible exhaustive search is needed for the full recovery of the secret prime. This is a first practical result of recovering a full secret of modular exponentiation which manipulates 512-bit RSA primitives with collision-based power analysis in a single attempt, where the previous attack demonstrates the result for 192-bit ECC primitive implementations. We also present a countermeasure against our attack which requires only one additional modular subtraction for the loop of square-and-multiply-always exponentiation algorithm. An experimental result for the effectiveness of our proposed countermeasure is presented.

Additive manufacturing (AM), a.k.a. 3D printing is increasingly used to manufacture functional parts of safety-critical systems. The AM's dependence on computerization raises the concern that the AM process can be tampered with, and a part's mechanical properties sabotaged. To address this threat, we propose a novel approach for detecting sabotage attacks based on trusted monitoring of the current delivered to each printer motor. The proposed approach offers numerous advantages: 1) it is non-invasive in a time-critical process, 2) it can be retrofitted in legacy systems, and 3) it can be air-gapped from the computerized components of the AM process, making simultaneous compromise more difficult. We evaluated the approach on five categories of toolpath command-level manipulations that impact the geometry of the 3D printed object. Our evaluation showed that all but one tested category of attacks can be reliably detected, even if a single toolpath command is modified.

Ring Lizard (RLizard) is a quantum-resistant public-key cryptosystem based on the ideal lattice. RLizard uses a sparse ternary polynomial, which facilitates implementation with lower complexity. The Lizard scheme's proposal for the National Institute of Standards and Technology's post-quantum cryptography standardization included its reference hardware design using the sparse ternary property; however, in this paper, we present the RLizard crypto-processor with the improved processing speed and security level against power analysis attacks. By additionally utilizing unused values for each memory access in the conventional RLizard crypto-processor, the processing speed of the proposed RLizard crypto-processors can increase by a factor of two or up to four times. The implementation results with three different FPGA devices show that the area overhead is approximately 50-100 flip-flops (FFs) and 50-300 lookup tables (LUTs), occupying approximately 2%-3% of the total area. The vulnerability to power analysis attacks and the proposed countermeasures were also analyzed. The experimental results prove the vulnerability of unprotected implementation, and the implementation results show that the masking and hiding countermeasures additionally require approximately 50-120 FFs and 100-360 LUTs. In addition, our idea can be applied to other ideal-lattice-based cryptosystems using a sparse binary or ternary polynomial, such as NTRU and Round5.

Embedded multi-core systems are implemented as systems-on-chip that rely on packet storeand-forward networks-on-chip for communications. These systems do not use buses or global clock. Instead routers are used to move data between the cores, and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such systems is very much facilitated using dataflow concepts. In this paper, we propose a methodology for implementing algorithms on dataflow platforms. The methodology can be applied to multi-threaded, multi-core platforms or a combination of these platforms as well. This methodology is based on a novel dataflow graph representation of the algorithm. We applied the proposed methodology to obtain a novel dataflow multi-core computing model for the secure hash algorithm-3. The resulting hardware was implemented in field-programmable gate array to verify the performance parameters. The proposed model of computation has advantages, such as flexible I/O timing in term of scheduling policy, execution of tasks as soon as possible, and self-timed event driven system. In other words, I/O timing and correctness of algorithm evaluation are dissociated in this paper. The main advantage of this proposal is ability to dynamically obfuscate algorithm evaluation to thwart side-channel attacks without having to redesign the system. This has important implications for cryptographic applications.

Mobile social networks (MSNs) are the networks of individuals with similar interests connected to each other through their mobile devices. Recently, MSNs are proliferating fast supported by emerging wireless technologies that allow to achieve more efficient communication and better networking performance across the key parameters, such as lower delay, higher data rate, and better coverage. At the same time, most of the MSN users do not fully recognize the importance of security on their handheld mobile devices. Due to this fact, multiple attacks aimed at capturing personal information and sensitive user data become a growing concern, fueled by the avalanche of new MSN applications and services. Therefore, the goal of this work is to understand whether the contemporary user equipment is susceptible to compromising its sensitive information to the attackers. As an example, various information security algorithms implemented in modern smartphones are thus tested to attempt the extraction of the said private data based on the traces registered with inexpensive contemporary audio cards. Our obtained results indicate that the sampling frequency, which constitutes the strongest limitation of the off-the-shelf side-channel attack equipment, only delivers low-informative traces. However, the success chances to recover sensitive data stored within a mobile device may increase significantly when utilizing more efficient analytical techniques as well as employing more complex attack equipment. Finally, we elaborate on the possible utilization of neural networks to improve the corresponding encrypted data extraction process, while the latter part of this paper outlines solutions and practical recommendations to protect from malicious side-channel attacks and keep the personal user information protected.

The password-based authenticated key exchange (PAKE) protocol is one of most practical cryptographic primitives for trusted computing, which is used to securely authenticate devices' identities and generate shared session keys among devices in insecure environments by using a short, human-memorable password. With the fast development of the Internet of Things (IoT), new challenges regarding PAKE have emerged. The traditional PAKE protocols are completely insecure in IoT environments, since there are many kinds of side-channel attacks. Therefore, it is very important to model and design leakage-resilient (LR) PAKE protocols. However, there has been no prior work on modeling and constructing LR PAKE protocols. In this paper, we first formalize an LR eCK security model for PAKE based on the eCK-secure PAKE model and the only computation leakage model. Then, we propose the first LR PAKE protocol by using Diffie-Hellman key exchange, LR storage (LRS) and LR refreshing of LRS appropriately and formally present a security proof in the standard model.