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In the 5G and beyond networks, low-latency digital signatures are essential to ensure the security, integrity, and non-repudiation of massive data in communication processes. The binary finite field-based elliptic curve digital signature algorithm (ECDSA) is particularly suitable for achieving low-latency digital signatures due to its carry-free characteristics. This paper proposes a low-latency and universal architecture for point multiplication (PM) and double point multiplication (DPM) based on the differential addition chain (DAC) designed for signing and verification in ECDSA. By employing the DAC, the area-time product of DPM can be decreased, and throughput efficiency can be increased. Besides, the execution pattern of the proposed architecture is uniform to resist simple power analysis and high-order power analysis. Based on the data dependency, two Karatsuba–Ofman multipliers and four non-pipeline squarers are utilized in the architecture to achieve a compact timing schedule without idle cycles for multipliers during the computation process. Consequently, the calculation latency of DPM is minimized to five clock cycles in each loop. The proposed architecture is implemented on Xilinx Virtex-7, performing DPM in 3.584, 5.656, and $7.453~\mu s$ with 8135, 13372, and 17898 slices over GF(2163), GF(2233), GF(2283), respectively. In the existing designs that are resistant to high-order analysis, our architecture demonstrates throughput efficiency improvements of 36.7% over GF(2233) and 9.8% over GF(2283), respectively.

This paper describes an N-path sub-GHz ultra-low power receiver exploiting an N-path notch filter topology in 90nm CMOS process. The receiver achieves the flexibility in the operating frequency due to an adjustable internal impedance matching network with an N-path notch filter. The receiver consists of two current-reused topologies, which greatly simplifies the structure and achieves ultra-low power consumption. Specifically, the receiver incorporates: 1) an amplifier with an N-path notch filter, which acts as the first stage of the receiver to provide an input impedance of $50~\Omega $ without an inductor. This input matching network is frequency flexible and adjustable to suit different frequencies of the input signal. Meanwhile, the N-path notch filter can suppress out-of-band interference to cope with limited frequency bands. 2) N-path passive mixers are reused for simultaneous filtering and down-conversion. 3) Amplifiers are frequency-division multiplexed to amplify both RF and baseband signals simultaneously. Finally, the receiver is fabricated in 90 nm CMOS and operates at 0.6 V supply voltage with a power consumption of $780~\mu \text{W}$ . The receiver achieves a conversion gain of 41.2 ± 3.2 dB, a noise figure of 5.7 ± 0.3 dB and an OB-IIP3 of 14.6 ± 0.5 dBm. The chip area of the implemented receiver is 0.08 mm2.

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

L-shaped array (LA) is traditionally used as two one-dimensional uniform linear arrays (ULAs) for two-dimensional direction of arrival (DOA) estimations. With elevation and azimuth angles estimated separately, the detectable source number is strictly limited by the number of elements in the ULAs. To increase the detection ability, in this paper, we propose to exploit the diff-sum co-array (DSCA) concept on the L-shaped array. As such, a virtual element in the quadrants of DSCA can be generated by only one pair of sensors in the LA. Therefore, it can acquire much higher number of degrees of freedom for DOA estimation. To further reduce the redundancy of elements on the horizontal and vertical axes of DSCA, an element moving strategy is proposed. It is proved that the DSCA can remain intact with any one or more physical sensors relocated to the centrosymmetric positions. Based on this strategy, a generalized L-shape array concept and a new configuration referred to as generalized L-shaped array with odd-even locations (GLA-OEL) are developed. For GLA-OEL, the number of sensor pairs with small spacing is as small as one, which dramatically reduces the mutual coupling of adjacent elements. Besides, with the same number of sensors, the GLA-OEL can generate much larger virtual uniform rectangular array in the DSCA. Simulations verify the superiorities of the proposed array in terms of detection performance and estimation accuracy.

This paper introduces a novel speed-oriented architecture of point multiplication in elliptic curve cryptography. A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication. A modified Montgomery Ladder algorithm that takes three clock cycles to calculate one input bit is proposed to best utilize hardware resources. A mixed-pipeline technique is used to balance the delay of different paths and increase frequency. The proposed architecture is implemented on GF(2163) and GF(2571), based on Xilinx Virtex-5 and Virtex-7 FPGA. For GF(2163), the design reaches 211 MHz, with 29309 LUTs, and 547 clock cycles or $2.6~\mu \text{s}$ latency on Virtex-5; 320.5 MHz, with 28911 LUTs and $1.7~\mu \text{s}$ latency on Virtex-7. For GF(2571), the design reaches 186 MHz, with 286400 LUTs, and 1813 clock cycles or $9.6~\mu \text{s}$ latency on Virtex-5; 267 MHz, 290001 LUTs and $6.79~\mu \text{s}$ latency on Virtex-7. The proposed design achieves the lowest latency among all existing works, and its performance is also among the top. Furthermore, it is demonstrated that the proposed architecture maintains a high speed for larger binary fields, making it more suitable to be implemented in large-bit-length platforms with a higher security level. Since the multiplier and its segments work in different bit-length and refer to different fields, the proposed architecture can also be upgraded to a reconfigurable design to support multiple-field point multiplication in the future.