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Manufacturing yield, overkill, and defect level can limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign the design margin such that the design meets specifications at several processes and environmental corners. However, checking only a few extreme corners limits performance more than the more rigorous statistical approach of computing manufacturing and quality figure of merit. On the other hand, the statistical approach requires transistor level simulation of hundreds or thousands of samples, not just a few corners, and hence is very time-consuming. This paper gives a way to sidestep the problem by characterizing each of many samples of building blocks once at the transistor level. The building blocks are scalable so that statistics are preserved when a building block is adjusted to the requirement of a higher level design. Many design scenarios may be rapidly explored by assembling and scaling the building block samples without SPICE simulation. A continuous-time low-pass filter design example is used to extract the requirements of the building block approach. The requirements include a method to assemble building blocks (biquad element for the example) into a filter design while preserving the statistics that would have been extracted by simulation of the entire filter at the transistor level. The assembly method for both linear and nonlinear response is proposed. more...