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In this letter, we examine the role of the Ti capping layer in HfO x -based resistive random access memory (RRAM) devices on the memory performance. It is found that with a thicker Ti capping layer, the fresh device initial leakage current increases and as a result, the forming voltage decreases. In addition, with a thin Ti layer of

In this letter, we report a miniaturization strategy for harvesting a low-frequency random vibration energy with a piezoelectric energy harvesting (EH) system utilizing coupled Helmholtz resonance and vortex shedding effect. This is made possible by transferring the low-frequency vibration energy into a pressurized fluid, which is in turn converted into predefined, pressure-independent high-frequency energy harvested by the device. The vibration-pressurized fluid conversion extends the device sampling frequency band; enables efficient harvesting of broadband low vibration frequencies with small form factor. Proof of concept of the proposed strategy has been demonstrated with an AlN-based MEMS EH, which delivered an output power density of 95.5 mW/cm3 under a constant input airflow at 4.2 lbf/in2 pressure.

The low-frequency noise (LFN) in the subthreshold region of both n- and p-type gate-all-around silicon nanowire transistors (SNWTs) is investigated. The measured drain-current noise spectral density shows that the LFN in this regime can be well described by the mobility-fluctuation model due to the volume-inversion conduction behavior, and the Hooge parameter is extracted. The LFN in the SNWTs with channels oriented in lang010rang and lang110rang directions is compared. It shows that the observed mobility enhancement in the lang010rang direction for p-type transistors leads to a corresponding increase of the LFN level in the lang010rang direction compared with that in the lang110rang direction.

In this letter, we present SONOS nonvolatile memory device with gate-all-around polycrystalline silicon (poly-Si) nanowire channel. The SONOS memory cell with 23-nm nanowire width, fabricated using top-down CMOS process, exhibits fast programming and erasing speed as well as improved subthreshold behavior of the transistor. Both the memory and transistor characteristics are dependent on the nanowire width-smaller the width, better the performance. The good device characteristics along with simple fabrication method make the poly-Si nanowire SONOS memory a promising candidate for future system-on-panel and system-on-chip applications.

Germanium (Ge) bipolar phototransistors with high-responsivity performance are demonstrated using a low-temperature selective Ge epitaxy process. Large photocurrent and optical response enhancement are achieved over a conventional p-i-n Ge photodetector, which is predominantly attributed to the current gain induced by transistor actions. When illuminated with a photon wavelength of 1.55 mum , a Ge phototransistor shows a large responsivity of ~ 2.0 A/W for a low operating bias VA of 1.0 V. Optical measurement results further show that good photoresponse could be achieved for a spectral range of 1.31-1.62 mum, making such a device a very promising option for optical detections in the near-infrared (including L -band) wavelength regime.

A high-performance In0.53Ga0.47As n-channel MOSFET integrated with a HfAlO gate dielectric and a TaN gate electrode was fabricated using a self-aligned process. After HCl cleaning and (NH4)2S treatment, the chemical vapor deposition HfAlO growth on In0.53Ga0.47As exhibits a high-quality interface. The fabricated nMOSFET with a HfAlO gate oxide thickness of 11.7 nm shows a gate leakage current density as low as 2.5 times 10-7 A/cm2 at Vg of 1 V. Excellent inversion capacitance was illustrated. Silicon implantation was self-aligned to the gate, and low-temperature activation for source and drain was achieved by rapid thermal annealing at 600degC for 1 min. The source and drain junction exhibited an excellent rectifying characteristic and high forward current. The result of an In0.53Ga0.47As nMOSFET shows well-performed Id-Vd and Id-Vg characteristics. The record high peak electron mobility of 1560 cm2/Vs has been achieved without any correction methods considering interface charge and parasitic resistance.

This letter demonstrates a way for modifying the effective work function Phim of a molybdenum (Mo) gate electrode by interface dipole engineering in a metal gate/high-k gate stack. N-type Mo gate Phim (~4.2 eV) was achieved on a HfLaO gate dielectric even after 950-degC rapid thermal annealing (RTA) due to the presence of a La-induced interface dipole layer. By alloying with ~14%-19% of aluminum (Al), the effective Mo gate Phim on HfLaO significantly increased by ~0.6 eV after 950-degC RTA. The incorporation of Al into the HfLaO gate dielectric was evident after the high-temperature anneal. The Phim modulation was attributed to Al-induced interface dipole formation, of which has opposite polarity to the La-induced dipole, at the high-k/SiO2 interface. This novel concept of employing two opposing interface dipoles in the same metal gate/high-k stack for Phim tunability would provide insights for future gate stack interface engineering.

This letter reports the first demonstration of an evanescent coupled germanium-on-silicon-on-insulator (Ge-on-SOI) metal-semiconductor-metal (MSM) photodetector with a novel silicon-carbon (Si:C) Schottky barrier enhancement layer. Through the insertion of a Si:C barrier layer between the metal/Ge interface, the hole Schottky barrier height phibh can effectively be enhanced to ~0.52 eV above the valence band edge. As a result, significant dark-current IDark suppression by more than four orders of magnitude was demonstrated, leading to an impressive IDark of ~11.5 nA for an applied bias VA of 1.0 V. Optical measurements performed at a photon wavelength of 1550 nm revealed the achievement of good internal responsivity and quantum efficiency of ~530 mA/W and 42.4%, respectively, making such a high-performance Ge-on-SOI MSM photodetector a promising option for optical communication applications.

This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 103 muA/mum), high Ion/Ioff ratio (~107), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si0.7Ge0.3) to channel (Si0.3Ge0.7) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (Gm) as compared to the homojunction planar device (Si0.7Ge0.3). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).

Si-waveguide-integrated lateral Ge p-i-n photodetectors using novel Si/SiGe buffer and two-step Ge-process are demonstrated for the first time. Comparative analysis between lateral Ge p-i-n and vertical p-Si/i-Ge/n-Ge p-i-n is made. Light is evanescently coupled from Si waveguide to the overlaying Ge- detector, achieving high responsivity of 1.16 A/W at 1550 nm with f3 dB bandwidth of 3.4 GHz for lateral Ge p-i-n detector at 5 V reverse bias. In contrast, vertical p-Si/i-Ge/n-Ge p-i-n has lower responsivity of 0.29 A/W but higher bandwidth of 5.5 GHz at -5 V bias. The higher responsivity of lateral p-i-n detectors is attributed to smaller optical mode overlap with highly doped Ge region as in vertical p-i-n configuration.

This letter reports for the first time on an electrically pumped silicon light-emitting device with a thin multilayer stacked amorphous silicon (alpha-Si, in thickness of 3-7 nm)/silicon nitride (~10 nm) structure. The observed photoluminescence (PL) is tunable from ~700 to ~670 nm, and intensity increases by decreasing the alpha-Si thickness. The PL intensity can be enhanced through postdeposition annealing at relatively low temperatures and a short annealing time (e.g., as optimized at 700degC/10min). Electroluminescence from devices that are built upon the proposed structure originates from electron-hole pair recombination, and the carrier injection mechanism is through Frenkel-Poole tunneling. Our proposed structure, being highly complimentary metal-oxide-semiconductor compatible, benefits from a low thermal budget process coupled with an accurate layer thickness control.

We demonstrate, for the first time, the application of dopant-segregation (DS) technique in metal-germanium- metal photodetectors for dark-current suppression and high-speed performance. Low defect density and surface smooth epi-Ge (~300 nm) layer was selectively grown on patterned Si substrate using two-step epi-growth at 400degC/600degC combined with a thin (~10 nm) low-temperature Si/Si0.8 Ge0.2 buffer layer. NiGe with DS effectively modulates the Schottky barrier height and suppresses dark current to ~10 -7 A at -1 V bias (width/spacing: 30/2.5 mum). Under normal incidence illumination at 1.55 mum, the devices show photoresponsivity of 0.12 A/W. The 3 dB bandwidth under - 1 V bias is up to 6 GHz.

For the first time, we demonstrate experimentally that using HfLaO high-kappa gate dielectric and vertical stacks of TaN/Ru metal layers, dual metal gates with continuously tunable work function over a very wide range from 3.9 to 5.2 eV, can be achieved after 1000 degC annealing required by a conventional CMOS source/drain activation process. The wide tunability of work function for this bilayer metal structure is attributed to metal interdiffusion during annealing and the release of Fermi level pinning between metal gates (Ru and TaN) and HfLaO. Moreover, this change is thermally stable and unaffected by a subsequent high temperature process.

This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., DeltaV OUT/DeltaV IN up to ~ 40 for V DD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.

Gate-all-around n-MOSFETs with Si-nanowire (~7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (~5 K to 295 K). IDS-VGS characteristics at low VDS (~50 mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about ~200 K. However, at high VDS, drain current reverts to typical temperature behavior, i.e., IDS increases with the reducing temperature due to the increase in phonon-limited mobility (muph)- It is inferred that, at low VDS the enhancement in muph at a reduced temperature could be possibly masked by the intersubband scattering on account of subband splitting due to quantum-confinement effects as indicated by subband calculations for nanowire structures.

This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme. High-kappa (HfO2 ~ 5 nm) and metal-gate (TaN ~ 100 nm) are evaluated on Si nanowires having ~5-7 nm diameter. While no significant mechanical effect is observed after high-kappa deposition, the TaN metal layer is found to viciously stretch and twist the straight wires. The wire lengths increase significantly (~3%), which suggests that the Si nanowires are subjected to large tensile strain ( > 4 GPa), assuming that the wires obey Hooke's law with Young's modulus ~150 GPa for bulk Si. Interestingly, the twisted nanowires maintained their physical continuity, as demonstrated by the excellent performance of the fully functional gate-all-around MOSFETs fabricated with the wires as channels.

Novel yttrium- and terbium-based interlayers (YIL and TbIL, respectively) on SiO2 and HfO2 gate dielectrics were employed for NMOS work function Phim modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phim of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) YIL and TbIL, respectively, on the SiO2 gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phim on SiO2 could also be tuned between the Si midgap and the conduction bandedge EC by varying the interlayer thickness. The achievement of NiSi Phim around 4.28 eV on the HfO2 gate dielectric using interlayer insertion makes this an attractive Phim modulation technique for Ni-FUSI gates on SiO2 and high-k dielectrics

In this letter, we investigate the long-term reliability characteristics of ultrathin HfO2 dielectrics on nitrided germanium for the first time. Stress-polarity dependence in charge trapping and time-dependent dielectric-breakdown (TDDB) characteristics has been observed in germanium nand p-type devices. The p-MOS devices exhibit severe charge trapping under stress, while no significant charge trapping and stress-induced leakage current were found in the n-MOS devices. In terms of operation-voltage projection for a ten-year lifetime, Vg=2.8 and -2.1 V is projected for the germanium p- and n-MOS devices, respectively, with an equivalent oxide thickness of 11 Aring. Compared to Si control samples, germanium devices show a comparable projected operation voltage, indicating that the TDDB for high-kappa dielectrics on nitrided germanium is not a concern. The stress-polarity dependence in germanium devices is believed to result from the asymmetrical band structure and the significant difference of the electric field strength across the gate dielectric between the positive and negative stress conditions

This letter correlates fast transient charging (FTC) in high-k gate dielectrics to variations in its oxygen content. Analysis of electrical and physical data suggests that the observed enhancement of FTC may be caused by reduction of the oxygen content in the high-k film due to O scavenging process induced by the HfSix metal electrode. A hypothesis correlating O scavenging from the high-k dielectric to O vacancy formation, which contributes to FTC, is proposed

For the first time, the random telegraph signal (RTS) and its corresponding flicker noise (1/f) were investigated in gate-all-around p-type Si-FinFETs. For a device with gate width of ~ 100 nm (fin height) and length of ~ 200 nm, the typical RTS capture/emission time constants were ~ 0.1-1 ms. Very large RTS amplitudes (DeltaId/Id up to 25%) were observed, which is an effect attributable to the extreme device scaling and/or interface quality of FinFETs. The estimated scattering coefficients (alpha~10-12-10-13 ) are found to be higher than typical values obtained from MOSFETs. These findings demonstrate the relevance of RTS for FinFET operation

The effective work function (EWF) extracted on terraced oxide structures by capacitance-voltage-based techniques was compared with the work function calculated from the barrier height extracted by current-voltage measurements. The results show a reasonable correlation-within /spl plusmn/ 0.1 eV-in the EWF values for various metal gate electrodes, validating both techniques for EWF extraction.

This letter reports on a device layer transfer (based on thermal bonding and grinding backside Si) process and device characteristics of Si MOSFETs on a flexible substrate, focusing mainly on the mechanical bendability of the device and resistance to fatigue. The results demonstrated a well-optimized bonding process, as indicated by the nearly indiscernible performance difference (e.g., subthreshold slope, V/sub th/, and I/sub dsat/) before and after the bonding of Si with the flexible substrate. The device characteristics indicate excellent bendability of Si MOSFETs on flexible substrate (e.g., for radius tested down to /spl plusmn/72 mm) and good immunity to fatigue (e.g., negligible performance drift tested up to /spl sim/10/sup 3/ bending cycles with a radius of /spl plusmn/126 mm). Results suggest the feasibility of this approach in achieving high-performance MOSFETs for applications in performance-sensitive and flexible electronics.

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.

In this letter, new endurance degradation behaviors in the bipolar resistive random access memory devices with multilayered HfOx/TiOx are reported for the first time, showing almost a constant resistance in low resistance state and a gradually reduced resistance in high resistance state (HRS). Further investigations into the dependence of HRSs degradation speed on switching voltage and temperature reveal that the degradation is attributed to the oxygen ion (O2-) loss effect during RESET process, which leads to the insufficient O2- supply for recombining the oxygen vacancies. Possible technical solutions are then proposed to improve the endurance performance.

Different HfOx-based resistive random access memory stacks with Ni-containing electrodes, including NiSi and Ni(Ge1-xSix), which can be easily formed on the source/drain of a transistor, are systematically investigated in this letter. The involvement of Ni (or NiOx formed) at the interface has been found very beneficial to good switching properties. Moreover, RESET current can be effectively reduced for silicide electrodes compared to the n+ -Si case, attributed to the formation of a thicker interfacial layer involving NiOx and/or GeOx. In addition, a well-controlled interfacial layer is believed to be very helpful for the switching uniformity improvement. All these observations suggest the prospect of a compact 1T-1R integration scheme with Ni-containing electrodes.

This letter investigates junctionless nanowire field-effect transistor (NWFET) (JL-NWFET) parameters such as piezoresistance and low-frequency noise (LFN) with respect to channel doping and gate bias. The JL-NWFET is piezoresistive, and its gauge factor (GF ) is increased from 24 to 47 by reducing the channel doping ten times from 6.7 × 1019 to 6.7 × 1018 cm-3. Significant variations of GF and LFN are observed when the JL-NWFET is operated from subthreshold to on-state regime, and resolution (minimum detectable strain) is improved four times compared to inversion-mode NWFET. The simple fabrication and superior resolution formulate JL-NWFET as a promising sensing element for miniaturized nanoelectromechanical sensors.

The variation of through-silicon-via (TSV) capacitance caused by nonuniform hot-spot heating can lead to spatial circuit performance variation; this effect is undesirable for 3-D IC design. Hence, stable TSV capacitance is desired to overcome this issue. In this letter, stable TSV capacitance is achieved by utilizing Al2O3-induced negative fixed charge (|Qf| = 7.44 × 1011 cm-2) at the Si-liner interface. This causes a positive shift in the flat-band voltage (ΔVFB = 6.85 V) and results in the TSV operating in the stable accumulation capacitance region within operating voltage of interests (~0-5 V). The leakage current density of the TSV with Al2O3 layer and PETEOS liner is improved by ~10× after annealing in forming gas (N2/H2) at 300 °C for 30 min.

Three-dimensional solenoids have been developed and demonstrated for the first time in stacking of through-silicon via chips. High-density microcoils (width, space, and depth with 24 turns) were completely filled with Cu. Eight high-density microcoil chips were stacked using a conductive adhesive. The inductance of the eight stacked high-density microcoil chips is measured to be at 0.9 MHz, and the maximum magnetic field reaches to 0.67 mT, as characterized by a magnetic field detector 2 mm above the cavity center of the coils. The eight stacked high-density microcoil chips achieved 66-h operation under continuous current (0.2 A) stress testing without failure. Two microcoil chips stacked using solder also completed 1000 thermal cycles (to 125) successfully with merely 3.7% resistance change.

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current ( ; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

We present n-type gate-all-around (GAA) junctionless nanowire field-effect transistor (JL-NWFET) along with low-frequency noise (LFN) with respect to channel doping and the gate bias voltage. Irrespective of doping level in the channel, which is the same as that of source/drain, the JL-NWFET shows approximately five orders of magnitude lower spectral noise than the inversion-mode counterpart. LFN in JL-NWFET is also found less sensitive to gate bias voltage and to the frequency. The superior LFN behavior in GAA JL-NWFET is attributed to the conduction of carriers inside the uniformly doped nanowire channel. JL-NWFET-based sensing elements can thus be suitable in physical transducers to maximize the detection limits.

The characteristics of piezoresistive silicon nanowires (SiNWs) under compressive strain as large as 1.7% are reported. The SiNW is embedded in a multilayered diaphragm structure consisting of silicon nitride and silicon oxide. After leveraging the high fracture stress and intrinsic tensile stress of silicon nitride layer to produce a flat diaphragm, we can create large compressive strain to the SiNW without damaging the diaphragm. The relationship between SiNW resistance change and applied strain is measured and investigated with 2-μm and 5-μm SiNWs for both scientific and practical points of view. This approach demonstrates the validity to reveal the SiNW properties under large strain, and the exploration provides good reference for future SiNW-based MEMS sensor design.

For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.

A vertical Si nanowire (SiNW) gate-all-around n-type MOSFET integrated with Ni fully silicided gate is presented. Devices are fabricated with 100 nm gate length on vertical SiNWs with diameters down to 50 nm using fully CMOS compatible top-down approach. Tunability of the threshold voltage (ΔVT ~ 0.3 V), which is vital in nanowire devices to make them suitable for circuit integration, has been achieved without impacting other electrical parameters (SS ;107). In addition, VT dependence on nanowire diameter is studied. The results indicate that multiple VT required in logic circuits can be implemented through different nanowire diameters with the same doping conditions for all devices.

A 2-D silicon phononic crystal (PnC) slab of a square array of cylindrical air holes in a 10-μm-thick freestanding silicon plate with line defects is characterized as a cavity-mode PnC resonator. A piezoelectric aluminum nitride (AlN) film is employed as the interdigital transducers to transmit and detect acoustic waves, thus making the whole microfabrication process CMOS compatible. Both the band structure of the PnC and the transmission spectrum of the proposed PnC resonator are analyzed and optimized using finite-element method. The measured quality factor (Q factor) of the microfabricated PnC resonator is over 1000 at its resonant frequency of 152.46 MHz. The proposed PnC resonator shows promising acoustic resonance characteristics for radio-frequency communications and sensing applications.

In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high Ion/Ioff ratio of >; 106, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced barrier lowering [(DIBL); ~50 mV/V] with a wire diameter of ~30 nm. Inverters have been successfully fabricated based on the poly-Si NW TFTs, exhibiting well-behaved transfer characteristics.

This letter reports on a junctionless silicon/oxide/nitride/oxide/silicon memory realized on vertical-Si-nanowire gate-all-around structures with two physical storage nodes per cell. Two physical bits per cell are electrically evaluated by studying the second bit effect and the program/erase speeds, endurance, and retention. The relaxed channel length limitation due to the vertical structure provides more tolerance to overcome the scaling-related reliability issues. In addition, the absence of junctions reduces the process complexity and cost, thus making this device more manufacturable with a very low thermal budget.

In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG) transistor with the same dielectric thickness. This effect can be very significant when the dielectric curvature is large as in practical NW devices. A high- k gate dielectric is more effective in suppressing the gate tunneling in CG transistors than in PG transistors.

In this letter, a significantly improved uniformity of device parameters (for cycle-to-cycle uniformity within one device and device-to-device uniformity), such as set voltage, reset voltage, and HRS and LRS resistance distributions, is successfully demonstrated on HfOx/TiOx multilayer (ML)-based resistive switching devices, as compared with HfOx-based single-layer device. In addition, the reported ML devices are free from forming process, which is greatly beneficial from the viewpoint of RRAM circuit operation. It is believed that both the Ti doping effect and the confinement of conduction filament within different dielectrics layers contribute to the improvement.

The retention failure of bipolar oxide-based resistive switching memory is investigated. A new physical model is proposed to elucidate the typical retention failure behavior of the oxide-based resistive switching memory with a sudden resistance transition, which is quite different from that of the traditional memories. In the new proposed model, the temperature- and bias-dependent failure probability and failure time of the devices can be quantified. A temperature- and voltage-acceleration method is developed to evaluate the retention of resistive switching memories.

In this letter, we report for the first time the degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments and TCAD simulation, we show that the drain current degradation is mainly induced by the interface traps and/or oxide charge located above the tunneling region, causing reduction of tunneling field and tunneling current. The interface traps mainly induce the degradation in transconductance, while the oxide charge essentially causes a threshold-voltage shift in TFETs. The results show that the interface-trap generation is dominant under a positive-bias stress, while the oxide-charge creation is important under an HC stress in n-TFETs.

Accurate modeling of stress-retarded orientation-dependent 2-D oxidation is carried out by matching the experimental and simulated oxide thicknesses of silicon FIN nanostructures over a wide range of temperatures and times in dry oxygen. Experimentally observed initial oxidation rate enhancement, orientation-dependent stress retardation, and self-limiting phenomena are modeled, and a new universal stress retardation parameter set is obtained for the first time. The new parameter set has been validated against oxidation experiments presented here and those reported in the literature. Furthermore, the new model is used to explore silicon nanowire shape engineering.

We report, for the first time, the reliability issues of tunneling field-effect transistors (TFETs) by experiments. We observed that the overall reliability performance of n-TFETs is very different from those of the conventional n-MOSFET. The degradation of n-TFETs under positive bias temperature instability (PBTI) stress is very large compared with the negligible degradation for the conventional n-MOSFET. The degradation of n-TFETs under hot-carrier stress is also larger than that in the conventional n-MOSFET and has a different temperature dependence. The shifts of the I d- V g curves under PBTI stress are not parallel in the strong inversion region as in the case of the conventional n-MOSFET. The different degradation behaviors are explained by different degradation mechanisms due to some inherent properties of TFETs.

In this letter, we demonstrate a multibit programmable vertical silicon nanowire (SiNW) SONOS memory using a top-down method. The flash devices realized on highly scaled squarish SiNW down to 20 nm in diagonal show much improved program/erase speed and window along with good retention and endurance characteristics as compared to the ones with a large dimension. The performance improvements with scaling of wire dimensions are attributed to the enhancement of the electric field in tunnel oxide and reduction in blocking oxide as a result of reduced radius of curvatures, particularly on the corners of the squarish wire.

In this letter, the electrical performance in terms of power conversion efficiency (PCE) of Si nanopillar (SiNP)-textured thin-film solar cell is investigated via simulation, where the SiNP physical dimensions were predetermined for optimized solar-energy absorption. Several key factors affecting PCE of the solar cell, e.g., the impact of Si quality in terms of minority carrier lifetime, emitter doping level, and emitter junction depth, is highlighted, and a practical guideline to design high-efficiency SiNP-textured thin-film solar cell is thus provided. The PCE of the structure under investigation can be significantly boosted, compared with the to-date reported Si thin-film solar cell.

The low-frequency (1/f) noise of gate-all-around silicon nanowire transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region. It shows that the gate electrodes have a strong impact on the 1/f noise of the SNWTs. The highest noise is observed in the SNWTs with a poly-Si gate, compared to their FUSI-gate counterparts. The observations are explained according to the number fluctuation with correlated mobility fluctuation theory by assuming that the correlated mobility scattering is better screened in the case of an undoped FUSI gate. However, the doped FUSI gate with silicidation-induced impurity segregation at the gate/SiO2 interface gives rise to extra mobility scattering.