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In this letter, we report on demonstrating a Schottky barrier diode (SBD) with high reverse blocking voltage by incorporating an ultra-wide bandgap semiconductor Al0.85 Ga0.15 N channel. Benefited from the lower activation energy of the Si in GaN, the net carrier concentration of Al0.85 Ga0.15N can be essentially enhanced to ${2}\times {10}^{{17}}$ cm−3 level with surface roughness of 0.33 nm. Due to the good material property, a reverse blocking voltage of 2 kV and room temperature ideality factor of 2.3 are demonstrated. Combined with the significantly improved on-current and on/off ratio of more than 106 when compared with other AlN SBDs, Al0.85 Ga0.15 N turns out to be a competitive AlN counterpart by considering the compromise among ultra-wide bandgap, dopant activation, and material property.

We present a novel hybrid dopant activation technique for n-type silicon–germanium (SiGe) to achieve high doping concentration and ultra-shallow junction at low temperature (≤500 °C) using rapid thermal annealing and pulsed green laser post-annealing (hybrid RTA-GLA). The hybrid RTA-GLA process achieved one of the highest surface and peak doping concentrations of $1.82\times 10^{\textsf {20}}$ cm−3 and $9.27\times 10^{\textsf {20}}$ cm−3, respectively, compared with low-temperature doping techniques for n-type SiGe. In addition, the n-type SiGe films doped by the hybrid RTA-GLA process provide ultra-shallow (

A Ge0.955Sn0.045 nMOSFET with a record high mobility of 440 cm2/V $\cdot $ s is demonstrated in this letter by a gate-first process. By low-temperature chemical vapor deposition, high-quality GeSn films were epitaxially grown. The ambipolar leakage is effectively suppressed by the low-thermal-budget microwave annealing (MWA) step. Furthermore, the peak mobility in the device after the MWA step is enhanced by a factor of two compared with those after rapid thermal annealing. This can be attributed to the weaker Coulomb scattering at the oxide interface after the MWA step, suggesting that MWA is effective for dopant activation and a better oxide interface quality at the same time.

Germanium n+/p junctions with high phosphorus dopant activation (>1020 cm−3) and minimal dopant diffusion were achieved by $P$ implantation and laser spike annealing (LSA) at temperatures ≥794 °C for 400 $\mu \text{s}$ . In addition, there is no evidence of any residual extended defectivity near the junction after LSA. The effect of F co-doping was also investigated, demonstrating the reduction in both diffusion and activation. The thermal stability and electrical characteristics of Ge n+/p junction activated by LSA were evaluated.

This letter investigates the high-frequency performance of trigate polycrystalline silicon thin-film trans- istors (poly-Si TFTs) using low temperature microwave annealing (MWA). MWA exhibits sufficient dopant activation efficiency, good short channel effect control, and a higher maximum oscillation frequency ( $f_{\mathrm {\mathbf {max}}})$ of poly-Si TFTs than does rapid thermal annealing. In addition, MWA can fabricate nanoscale devices. Poly-Si TFTs with short channel annealed by microwave reveals better high-frequency performance and switching characteristics.

We report high performance Ge p(+)/n junctions using a single, cryogenic (-100 degrees C) boron ion implantation process. High activation >4 x 10(20) cm(-3) results in specific contact resistivity of 1.7 x 10(-8) Omega-cm(2) on p(+)-Ge, which is close to ITRS 15 nm specification (1 x 10(-8) Omega-cm(2)) and nearly 4.5x lower than the state of the art (8 x 10(-8) Omega-cm(2)). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p(+)/n junctions can pave the way for future high mobility Ge p-MOSFETs.

A high-performance In0.53Ga0.47As n-channel MOSFET integrated with a HfAlO gate dielectric and a TaN gate electrode was fabricated using a self-aligned process. After HCl cleaning and (NH4)2S treatment, the chemical vapor deposition HfAlO growth on In0.53Ga0.47As exhibits a high-quality interface. The fabricated nMOSFET with a HfAlO gate oxide thickness of 11.7 nm shows a gate leakage current density as low as 2.5 times 10-7 A/cm2 at Vg of 1 V. Excellent inversion capacitance was illustrated. Silicon implantation was self-aligned to the gate, and low-temperature activation for source and drain was achieved by rapid thermal annealing at 600degC for 1 min. The source and drain junction exhibited an excellent rectifying characteristic and high forward current. The result of an In0.53Ga0.47As nMOSFET shows well-performed Id-Vd and Id-Vg characteristics. The record high peak electron mobility of 1560 cm2/Vs has been achieved without any correction methods considering interface charge and parasitic resistance.

We report for the first time, the use of pulsed laser annealing (PLA) on multiple-gate field-effect transistors (MuGFETs) with silicon-carbon (Si1-xCx) source and drain (S/D) for enhanced dopant activation and improved strain effects. Si1-xCx. S/D exposed to consecutive laser irradiations demonstrated superior dopant activation with a ~60% reduction in resistivity compared to rapid thermal annealed S/D. In addition, with the application of PLA on epitaxially grown Si0.99C0.01 substitutional carbon concentration Csub increased from 1.0% (as grown) to 1.21%. This is also significantly higher than the Csub of 0.71% for rapid thermal annealed Si0.99C0.01 S/D. With a higher strain and enhanced dopant activation, MuGFETs with laser annealed Si0.99C0.01 S/D show a ~53% drain-current improvement compared to MuGFETs with rapid thermal annealed Si0.99C0.01 S/D.

In this letter, low-temperature (480°C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.

In this letter, co-implantation of P and Sb dopants into NiGe film is first proposed to improve the characteristic of NiGe/Ge contact. Through this technique, obvious enhancement of NiGe thermal stability is achieved. The surface morphology of NiGe film even keeps smooth and flat after post-germanidation annealing up to 600 $^{\circ}{\rm C}$ . The current characteristics of the formed NiGe/p-Ge diodes are also improved, exhibiting better rectifying performance. It is believed that the improved interface quality and the enhanced dopant activation contribute to these improvements. Therefore, this technique shows great potential for high performance Ge device technology.

A novel insulated gate bipolar transistor (IGBT) featuring thin-wafer processing and a combined dopant activation laser annealing and contact metal laser sintering is presented. The device concept includes a new back-side boron anode (collector) activation process by laser annealing through a titanium layer to enhance the absorption of the deposited energy from the laser beam. This technology enables improved activation control of the anode injection efficiency for thin-wafer-based IGBTs rated normally below 1700 V. The IGBT concept will therefore be provided with a wider range of performance options on the loss technology curve when compared to state-of-the-art devices processed with conventional activation techniques.

Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, during conventional fixed-frequency microwave heating, standing wave patterns can be established in the microwave processing chamber, resulting in nodes and antinodes over the processing area, resulting in thermal variations over the process wafer. In this letter, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency microwave anneal are studied. The composition, number, and spacing of susceptor wafers were varied in a systematic fashion in these experiments.

It is important for nanoscale transistors to have abrupt junctions, which are difficult to achieve via high-temperature anneals of implanted semiconductor layers due to undesired dopant diffusion. The use of a single-frequency microwave cavity applicator, along with a SiC-Alumina susceptor/assistor, is suggested as an alternative postimplantation process. Secondary ion mass spectroscopy analysis of microwave-annealed As-implanted Si samples show minimal diffusion, compared to rapid thermal annealed samples. Cross-sectional transmission electron microscopy and Raman spectroscopy confirm damage repair and Si recrystallization upon low-temperature microwave annealing (up to 650°C). Ion channeling and sheet resistance measurements validate dopant relocation and activation. The susceptor is used to provide surface heating to the high-atomic-number Z implanted sample to enable it to absorb microwaves and thereby recrystallize through volumetric heating.

Highly activated n-type dopant is essential for n+/p germanium diodes which will be in use for source/drain regions in Ge n-MOSFET as the geometry scaling proceeds. This letter has investigated a combination of ion implantation of Sb in Ge and subsequent laser annealing, which resulted in highly activated Sb beyond 1020 cm-3. Well-behaved Sb-doped nv/p Ge diode I-V characteristics have been demonstrated combined with TEM, SIMS, and spreading resistance profiling characterization.

Highly activated n-type dopant is essential for n+ /p germanium diodes which will be in use for source/drain regions in Ge n-MOSFETs as geometry scaling proceeds. Rapid thermal annealing of coimplanted P and Sb in Ge has provided n-type dopant activation beyond 1 × 1020 cm-3. However, there are limited reports on the electrical characteristics of these junctions. This letter has investigated the temperature-dependent diode I-V characteristics and contact resistance of metal-n+ Ge contacts. Well-behaved n+ /p Ge diodes (Ion/Ioff >; 105 and η

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.

Below 360°C, we demonstrate germanium (Ge) n+/p junction diode and n-channel Ge metal-oxide-semiconductor field-effect transistor (MOSFET) with a low temperature Al/Al2O3/GeO2 gate stack for monolithic 3-D integration using a metal-induced dopant activation (MIDA) technique. In particular, the cobalt (Co) MIDA phenomenon is investigated on Ge damaged by an implantation process. Shallow (~100 nm) source/drain junctions with very low resistivity (5.2 × 10-4 Ω-cm) are then achieved at very low temperature by the Co MIDA technique. Consequently, high diode and transistor current on/off ratios (~104 and ~103, respectively) are obtained in this n-channel Ge MOSFET.

Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120°C to 140°C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150°C reduction in maximum temperature at the same activation concentration (about 2 × 1019 cm-3) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.

We report the enhanced performance of Ge nanowire (NW) tunneling field-effect transistors (TFETs), realized using a millisecond flash-assisted rapid thermal process (fRTP) for dopant activation. The electrical characteristics of our fRTP-activated NW TFETs exhibit maximum drive currents up toImax ~ 28 μA/μm at Vdd = -3 V and improved subthreshold swings. By comparison, NW TFETs realized using conventional RTP for dopant activation show an order of magnitude lower current. We attribute these findings to a more abrupt doping profile at the tunnel junction, owing to reduced dopant diffusion and improved dopant activation.

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

We demonstrate an abrupt and box-shaped n+/p junction in Ge with a high level of activation of n-type-dopant phosphorus (P) using in situ doping during epitaxial growth. The temperature dependence of dopant activation was investigated associated with the shallower and abrupt junction formation. In addition, we have fabricated high-performance Ge n+/p-junction diodes at 400degC-600degC, based on the in situ doping technique. Excellent diode characteristics having a 1.1 times 104 on/off ratio and a high forward current density (120 A/cm2 at 1 V) are obtained in an n+/p diode at 600-C in situ doping.

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal-oxide-semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.

High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 mOmegaldrcm2) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.

The p-channel impact-ionization nanowire multiple- gate field-effect transistors (I-MuGFETs or I-FinFETs), which have a multiple-gate/nanowire-channel architecture, were demonstrated. The superior gate-to-channel coupling reduces the breakdown voltage VBD for enhanced device performance. For the first time, an in situ doped source was incorporated with the impact-ionization MOS transistor. The in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces VBD and enhances the on-state current Ion. An additional improvement was also achieved by incorporating a strained Si1-yCy impact-ionization region (I-region) and an in situ doped Si1-yCy source, leading to reduction in Vbd and enhancement in Ion. This is due to strain-induced reduction of the impact-ionization threshold energy Eth. Furthermore, an excellent subthreshold swing of below 3 mV/decade at room temperature was achieved for all devices.

The authors report on the novel MOSFETs that were fabricated on thin relaxed Ge epitaxial layers grown on Si substrates. With controlled epi-Ge thickness, selectively activated shallow source/drain (S/D) junctions are formed using low dopant activation energy of Ge. The Ge epitaxial layers determine the effective S/D junction depth by selectively activating S/D implantations only in the Ge layers, while suppressing activation in the Si substrates. Low junction leakage current and capacitance are also achieved by forming S/D junctions in Si substrates as well as in Ge layers with controlled epi-Ge thickness. With this technique applied to Ge-on-Si epitaxial layers, Ge pMOSFETs showed an improvement in short channel effects and junction characteristics.

This letter investigates the feasibility of adjusting the work function (WF) of TaN metal gate by intermixing (InM) of ultra-thin TaN/Metal stacks at high temperature. This could be useful for the integration of dual-WF metal gates in a gate-first CMOS process without exposing gate dielectric during metal-etching process. TaN/Tb and TaN/Ir stacks were studied, and it is found that the WF of TaN can be readily modulated through metal InM in TaN/Tb stack after high-temperature treatment (~1000 degC), which simulates the source/drain dopant activation process in a gate-first CMOS process. Factors affecting the InM process will be discussed. Successful transistor threshold voltage adjustment by ~300 mV on high-kappa HfTaON/HfO2 dielectrics has also been demonstrated in TaN/Tb stack using this technique

Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO/sub 2//SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V/sub th/, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.

A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dopants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature processing.

Electromagnetic induction heating (EMIH) is a novel rapid thermal processing technique that uses microwave and radio frequency (RF) radiation to directly heat silicon wafers. Heating rates of 125/spl deg/C/s have been achieved and 75 mm diameter wafers have been heated above 1000/spl deg/C using only 950 W of power. EMIH has been used to activate shallow implanted dopants with minimal diffusion of the junction depth. It is speculated that the exposure of the wafer to intense electric fields during the anneal may provide an additional driving force for dopant activation, allowing for higher activation at lower temperatures. Post-anneal junction depths less than 25 nm with sheet resistances between 700 and 1000 ohms/square have been achieved without the use of a controlled low oxygen ambient. The EMIH Rs-Xj curve penetrates the SEMATECH 100 nm technology box and with further optimizations may satisfy the 70 nm technology node.

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation.

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-/spl mu/m p/sup +/-n junctions. Among the 2/spl times/10/sup 15/ cm/sup -2/ BF/sub 2/ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal.

Poly-Si/sub 0.8/Ge/sub 0.2/-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si/sub 0.8/Ge/sub 0.2/-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO/sub 2/ interface and therefore improved PDE were also found in boron-implanted poly-Si/sub 0.8/Ge/sub 0.2/-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si/sub 0.8/Ge/sub 0.2/ gate technology with regard to the tradeoff between boron penetration and poly-gate depletion.

This work applied, for the first time, plasma immersion ion implantation (PIII) for source/drain doping on low-temperature processed polysilicon thin-film transistors (poly-Si TFTs). Experimental results indicate that PIII doping can provide adequate dopant concentration and junction depth for source/drain. In addition, H/sub 2/-diluted phosphorus PIII can promote dopant activation more efficiently during RTA at 600/spl deg/C than with conventional ion implantation (II) technology. The excellent characteristics of PIII doped poly-Si TFTs resemble those of conventional II doped ones.

The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon.

Boron penetration through thin gate oxide down to 17 /spl Aring/ is investigated in this work. Boron penetration is characterized by the amount of flat band shift in a MOS capacitor. The effective diffusion coefficient of boron in these thin oxides is found to be higher than in thicker oxides. The introduction of a moderate dose of fluorine (1/spl times/10/sup 15/ cm/sup -2/) during gate doping enhances boron penetration in these thin oxides. Compared to as-deposited polycrystalline silicon (poly-Si), crystallized amorphous silicon (/spl alpha/-Si) films display slower boron diffusion in the gate and reduce enhancement of boron penetration due to fluorine. However, crystallized /spl alpha/-Si gate also reduces the amount of dopant activation and leads to extra gate depletion. The tradeoff between dopant activation and boron penetration is discussed.

An experimental study of the p-type ion dopant BF 2 + in silicon molecular beam epitaxy (MBE) is described. BF 2 + was used to dope MBE layers during growth to levels ranging from 1 × 1016/cm3to 4 × 1018/cm3over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 1016/cm3in all cases. Diffused p-n junction diodes fabricated in BF 2 +-doped epitaxial material showed hard reverse breakdown characteristics.