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In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the ${V}_{\text {TH}}$ instability of p-GaN gate HEMTs. As the ${I}_{\text {D}}$ - ${V}_{\text {G}}$ sweeping time deceases from 5 ms to $5~\mu \text{s}$ , the ${V}_{\text {TH}}$ dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6 mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the ${V}_{\text {TH}}$ features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible ${V}_{\text {TH}}$ shift and hysteresis, proving the ${V}_{\text {TH}}$ instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the ${V}_{\text {TH}}$ instability is verified by a GaN circuit under switching stress. The ${V}_{\text {TH}}$ instability under different sweeping speed uncovers the fact that the high ${V}_{\text {TH}}$ by conventionally slow DC measurements is probably artificial. The DC ${V}_{\text {TH}}$ should be high enough to avoid HEMT faulty turn-on. [ABSTRACT FROM AUTHOR]

In this letter, we identified a dominant buffer trapping causing a bias-dependent dynamic R\mathrm{\scriptscriptstyle ON} for AlGaN/GaN Schottky barrier diodes (SBDs) fabricated on a C-doped AlGaN buffer as back-barrier. Current transient measurements at various temperatures were performed simultaneously on an AlGaN/GaN SBD and a transmission line model (TLM) structure based on the AlGaN/GaN heterojunction. During the stress of the TLM structure, the two Ohmic contacts are biased at the same voltage forming an equipotential surface while creating a uniform vertical electrical field to induce buffer trapping. We extracted the same dominant trap level of EC-0.60 eV from the current transient spectroscopy on both the AlGaN/GaN SBD and the TLM structure after stressing at −100 V, indicating that the increase in the dynamic R\mathrm{\scriptscriptstyle ON} of the diode is due to the electron trapping in the buffer layers. More electron filling of this buffer trap occurs at higher stressing voltages (from −50 to −200 V), which reflects in an enhanced current-transient amplitude at the same time-constant under higher stressing voltages. [ABSTRACT FROM PUBLISHER]

As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semianalytical model, and we propose the In~Ga1~As-source silicon-TFET as p-TFET. This design is partitularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs. [ABSTRACT FROM AUTHOR]

A method for extracting parameters of weakly Fermi-level pinned germanium (Ge) capacitors is introduced. This method makes progress toward a more generally valid reliable interface state parameter extraction. Such a general method is needed to evaluate and explain the behavior of Ge MOS capacitors, which show characteristics deviating considerably from silicon. The encountered weak pinning confirmed by the new extraction method explains the degraded Ge nMOSFET performance. [ABSTRACT FROM AUTHOR]

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3/GeO2/Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise. [ABSTRACT FROM PUBLISHER]

Random telegraph noise in resistive switching memory devices is governed by two distinct mechanisms—oxygen vacancy perturbations in the filament as well as the electron trapping–detrapping phenomenon. In this letter, we focus on the dominant role of vacancies in governing the stability of the filament in the high resistance state and characterize the dependence of the read disturb voltage (VDIST) on the depth of the reset level during switching. Our slow voltage ramp read disturb tests at different reset levels indicate the possibility of filamentary instability even for read voltages lower than the standard value of 0.10 V. These experimental trends can be well explained using the quantum point contact model for conduction in the filament, as deeper reset levels induce very steep potential gradients at the two ends of the constriction that make the filaments highly unstable and susceptible to structural modifications due to vacancy generation and/or transport during memory read operation. [ABSTRACT FROM PUBLISHER]

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high-k devices with TaN/ TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness. [ABSTRACT FROM AUTHOR]

Performance and negative-bias temperature instability (NBTI) on atomic-layer-deposited HfSiON metal-gated pMOSFETs are investigated. The impact of nitrogen incorporation either with plasma nitridation or NH3 anneal is studied and compared to the nonnitrided stacks. The capacitance equivalent thickness reduction that is observed in nitrided stacks is compensated by the slight decrease of the hole mobility for the same gate overdrive, resulting in no improvement of the performance. On the other hand, it is shown that nitridation strongly enhances NBTIs in these devices. Based on these results, the necessity of nitrogen incorporation in thin HfSiON/metal gate stacks should be reconsidered. [ABSTRACT FROM AUTHOR]

Reports on findings in the relation between channel hot-carrier degradation and gate-oxide breakdown in short-channel n-metal oxide semiconductor field-effect transistors. Reduction of the time-to-breakdown in the hot carrier regime; Role of the oxide electric field as a determinant in the oxide breakdown process.