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We demonstrate the effect of SF6 plasma passivation with a ZnO interlayer in a metal-interlayer-semiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metal-induced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF6 plasma treatment and inserting a thin ZnO interlayer, respectively. Specific contact resistivity exhibits $\sim 10^{4} \times $ reduction when the GaAs surface is treated with SF6 plasma, followed by ZnO interlayer deposition, compared with the Ti/n-GaAs ( $\sim 2 \times 10^{18}$ cm $^{-3}$ ) S/D contact. This result proposes the promising non-alloyed S/D ohmic contact for III–V semiconductor-based transistors.

We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal–interlayer–semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs ( $\sim 2 \times 10^{18}$ cm $^{-3})$ structure exhibits a $\sim 1660\times $ reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.

We demonstrate Fermi-level unpinning and contact resistance reduction by surface passivation using SF6 plasma treatment of a metal/germanium (Ge) contact. A specific contact resistivity ( $\rho _{\mathbf {c}})$ of 1.14 $\times 10^{\mathrm {\mathbf {-3}}}~\Omega \cdot $ cm $^{\mathrm {\mathbf {2}}}$ and 0.31 eV of Schottky barrier height is achieved for a Ti/SF6-treated n-type Ge (n-Ge) ( $N_{\mathbf {d}}=$ 1 $\times 10^{\mathrm {\mathbf {17}}}$ cm $^{\mathrm {\mathbf {-3}}})$ contact, exhibiting 1700 times $\rho _{\mathbf {c}}$ reduction from a Ti/nontreated n-Ge contact. A convenient and effective passivation process of the Ge surface is presented to alleviate Fermi-level pinning at metal/Ge contact and lower source/drain contact resistance of Ge n-type field-effect transistors.

We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n+-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal-semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S S/D structure with n+-IL provides much lower contact resistivity, resulting in $\sim 5 \times $ lower contact resistivity than $1\times 10^{\mathrm {\mathbf {-8 }}}~\Omega $ - $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ , specified in International Technology Roadmap for Semiconductors. In addition, we found that the M-I-S structure with n+-IL remarkably suppresses the sensitivity of contact resistivity to S/D doping concentration.

We demonstrate contact resistivity reduction by inserting an Ar plasma-treated TiO2− x heavily doped interfacial layer to metal/semiconductor contact to overcome a Fermi-level pinning problem on germanium (Ge). A specific contact resistivity of \(3.16 \times {10}~^{\mathrm {-3}} \Omega \cdot {\rm cm}^{2}\) on moderately doped n-type Ge substrate \((6\times 10^{16}{\rm cm}^{\mathrm {-3}})\) was achieved, exhibiting \(\times 584\) reduction from Ti/Ge structure, and \(\times 11\) reduction from Ti/undoped TiO2/Ge structure. A novel doping technique for TiO2 interfacial layer at low temperature using Ar plasma was presented to lower \(S/D\) contact resistance in Ge n-MOSFET.

We present a new model to demonstrate the effect of heavily doped interfacial layer (IL) insertion on contact resistivity reduction in metal-germanium (Ge) structure. It is found that the doping of IL results in lowering Schottky barrier of Ge significantly, and based on this lowering effect, a metal-IL-semiconductor model is newly proposed. From this model, the abrupt reduction of contact resistivity is observed in heavily doped condition as IL thickness is increased, and the minimum contact resistivity for 1 × 10 20 cm -3 doping concentration is reduced by ×25 compared with that of undoped one. These results are promising toward enhancing the device performance of Ge MOSFET, which is for sub-22-nm CMOS technology.

A metal nitride-interlayer-semiconductor source/drain (MN-I-S S/D) model is newly proposed to investigate the effect of tantalum nitride (TaN) on the specific contact resistivity ( $\rho _{c}$ ) of an MN-I-S S/D with an undoped interlayer (undoped-IL) or a heavily doped IL (n+-IL) in sub-10-nm n-type Ge FinFETs. In this model, the workfunction variation of TaN was considered following the Rayleigh distribution. Compared with MN-I-S structures with an undoped-IL, structures with an n+-IL generate much lower $\rho _{c}$ values (i.e., $\sim 2 \times 10^{{\mathbf {-9}}}\Omega \cdot \text {cm}^{2}$ ) and are less prone to variation. In addition, the impact of $\rho _{c}$ variation on device performance is investigated using 3-D technology computer aided design simulation for undoped or heavily doped ILs in MN-I-S S/D structures. MN-I-S S/Ds with an n+-IL can achieve much lower current variation and a higher ON-state drive current.