Search

A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type HfO\rm{x}-based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations using a current crowding effect This model is a semiempirical model that can simultaneously match both dc and ac characteristics of HfO\rm{x}-based ReRAM devices. [ABSTRACT FROM PUBLISHER]

In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field region, which means weaker electric field dependence, led to an underestimation of lifetime. This result was attributed to a filled trap cluster at a specific trap energy level, locally reducing the oxide electric field. Thus, different lifetimes can be projected depending on stress bias. Maintaining a PBTI stress bias range below this trap energy level is recommended for accurate projections. [ABSTRACT FROM PUBLISHER]

In this letter, we propose a model based on noise analysis for the filamentary switching mechanism in resistance random access memory having \ZrOx/\HfOx bilayer stacks. From the noise analysis results, we concluded that the current flowing during high-resistance state can be described as a trap-assisted current that flows through traps. It has been hypothesized that these traps are the cause of the instability of device parameters. To validate this, the noise analysis results of large-area devices were compared with those of small-area devices. As a consequence, we improved the uniformity of device parameters. [ABSTRACT FROM AUTHOR]

We investigated the effect of scaling down the device area of \WOx resistive random-access memory (RRAM) devices on their switching characteristics. Device dimensions were successfully scaled down to 50 nm using a via-hole structure with additional \Al2\O3 sidewall process. As compared to the microscale devices, the nanoscale devices exhibited a distinct switching mechanism and better memory performance, such as improved switching uniformity, larger memory window, and stable endurance characteristics for up to \10^7 cycles. This improvement can be explained by a uniform interfacial switching mechanism in nanoscale device; this is in contrast with the defect-induced filamentary switching mechanism observed in microscale devices. In this way, the intrinsic switching properties of RRAMs were obtained by scaling down of the device area, indicating that RRAMs hold considerable promise for future applications. [ABSTRACT FROM AUTHOR]

We investigated the generation and recovery process of traps in pMOSFETs under negative-bias temperature (NBT) stress by using pulsed and dc measurements. The behavior of generated traps was studied as a function of applied body bias (VB). The fast components induced with the application of a positive VB were independent of measurement time (tm), while the results from devices with no applied VB showed a strong dependence on tm. This suggests that the fast components of additional traps generated by a positive VB can be attributed to interface states (Nit) at the Si/SiO2 interface. Based on the results of recovery characteristics with an intentional measurement delay, the recovery of Nit is relatively slow, initiating on the scale of a few milliseconds. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (Nit) from that of oxide traps (Not) to NBTI behavior by varying the measurement time (tm) and the delay time (tR). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the Not in high-k dielectric was more responsible for the NBTI behavior than the Nit, but the contribution of Nit to NBTI increased as the stress continued because the generation rate of Nit was higher than that of Not. [ABSTRACT FROM AUTHOR]