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We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positive-bias temperature stress (VGS = +20 V, VDS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS = -20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (-11.1 V). However, it remains as small as -0.7 V for the DG TFT. [ABSTRACT FROM AUTHOR]

A Ga-In-Zn-O thin-film transistor with double-gate structure is reported. Enhancement-mode operation that is essential to the constitution of a low-power digital circuitry is easily achieved when the upper and lower gate electrodes are tied together. The saturation mobility and the subthreshold swing are improved from 3.65 cm2/(V · s) and 0.44 V/dec to 18.9 cm2/(V · s) and 0.14 V/dec, respectively, compared with the single-gate structure. We can modulate the threshold voltage of either gate by adjusting the bias on the other gate. [ABSTRACT FROM AUTHOR]